GPU ACCELERATED ADDRESS TRANSLATION FOR GRAPHICS VIRTUALIZATION

• US 20140354667A1
• Filed: 12/21/2011
• Published: 12/04/2014
• Est. Priority Date: 12/21/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lin, Yunbiao, Du, Jianghong
• Granted Patent: US 9,672,583 B2
• Time in Patent Office: Days
• US Class Current: 345/568
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing GPU (Graphics Processing Unit) accelerated address translation for graphics virtualization. In one embodiment, such a system includes a main memory having a plurality of machine physical addresses; a graphics processor unit having graphics memory therein; an address translation service integrated with the graphics processor unit; a hypervisor to manage one or more guest machines; wherein the hypervisor is to configure a lookup table within the graphics memory of the graphics processor unit; and further wherein the address translation service of the graphics processor unit is to translate a guest physical address for one of the one or more guest machines to a corresponding machine physical address within the main memory. Such a graphics processor unit may be implemented separate from a system, for example, embodied within a silicon integrated circuit.

Claims

1. A system comprising:

a main memory having a plurality of machine physical addresses;

a graphics processor unit having graphics memory therein;

an address translation service integrated with the graphics processor unit;

a hypervisor to manage one or more guest machines;

wherein the hypervisor to configure a lookup table within the graphics memory of the graphics processor unit; and

wherein the address translation service of the graphics processor unit to translate a guest physical address for one of the one or more guest machines to a corresponding machine physical address within the main memory.

2. The system of claim 1, further comprising:

one or more graphics virtualization registers;

wherein the one or more graphics virtualization registers inform the graphics processor unit that one of the guest machines have been assigned to the graphics processor unit by the hypervisor.

3. The system of claim 2, wherein the one or more graphics virtualization registers further identify where the lookup table is located for the assigned guest machine.

4. The system of claim 1, further comprising:

a graphics virtualization determination component integrated within the graphics processor unit;

wherein the graphics virtualization determination component is to determine whether or not the graphics processor unit is operating within a virtualization environment on behalf of one of the guest machines;

wherein the graphics processor unit to engage the address translation service when operating within the virtualization environment; and

wherein the system to implement logical memory address to guest physical address translation without engaging the address translation service of the graphics processor unit when the graphics processor unit is not operating within the virtualization environment.

5. The system of claim 1, wherein the hypervisor to engage the address translation service of the graphics processor unit by:

configuring one or more graphics virtualization registers to inform the graphics processor unit that one of the guest machines have been assigned to the graphics processor unit by the hypervisor; and

passing a Guest physical Frame Number (GFN) to the graphics processor unit for translation by the address translation service to a Machine Frame Number (MFN), wherein the GFN represents the guest physical address for one of the one or more guest machines and wherein the MFN represents the machine physical addresses within the main memory corresponding to the guest physical address.

6. The system of claim 1, wherein:

an address translation service integrated with the graphics processor unit retrieves Guest physical Frame Number (GFN) to Machine Frame Number (MFN) mappings from the lookup table in the graphics memory.

7. The system of claim 6, wherein:

the address translation service retrieves the GFN to MFN mappings through a Translation Lookaside Buffer (TLB) integrated within the graphics processor unit; and

wherein the TLB provides an indexable cache on behalf of the address translation service of the graphics processor unit.

8. The system of claim 1:

wherein the hypervisor comprises a virtual machine manager; and

wherein the one or more guest machines comprise one or more virtual machines.

9. The system of claim 1, further comprising:

a separate and distinct central processor unit communicably interfaced with the graphics processor unit via a system bus;

wherein the central processing unit lacks dedicated hardware circuitry to perform address translation of guest physical addresses to machine physical addresses.

10. The system of claim 1, wherein the graphics processor unit comprises a silicon integrated circuit type graphics processor unit.

11. The system of claim 1, wherein the graphics processor unit comprises a microprocessor within a tablet computing device or a smart phone or one of a plurality of microprocessors integrated within the tablet computing device or the smartphone.

12. The system of claim 11, wherein the tablet computing device or the smartphone comprises a separate and distinct central processing unit communicatively interfaced with the graphics processor unit within the tablet computing device or the smartphone;

and

wherein the central processing unit lacks dedicated hardware circuitry to perform address translation of guest physical addresses to machine physical addresses.

13. The system of claim 1:

wherein the graphics memory comprises shared graphics memory; and

wherein the hypervisor to configure the lookup table within the graphics memory of the graphics processor unit comprises the hypervisor to write the lookup table into the shared graphics memory of the graphics processor unit.

14. The system of claim 1:

wherein the hypervisor to configure the lookup table within the graphics memory of the graphics processor unit comprises the hypervisor to instruct the graphics processor unit to retrieve and store the lookup table;

wherein the graphics processor unit to issue a Direct Memory Access (DMA) request to fetch the lookup table; and

wherein the graphics processor unit to store the lookup table in the graphics memory.

15. The system of claim 1:

wherein the hypervisor to issue a lookup table update to the graphics processor unit; and

wherein the graphics processor unit to responsively update the lookup table in the graphics memory.

16. A method comprising:

managing, via a hypervisor, one or more guest machines on a system;

configuring a lookup table with a mapping of guest physical addresses for the one or more guest machines to corresponding machine physical addresses;

transferring the lookup table to a graphics memory of a graphics processor unit;

receiving an access request to a main memory of the system from one of the guest machines, wherein the access request specifies a guest physical address;

engaging an address translation service internal to the graphics processor unit by passing the guest physical address to the graphics processor unit; and

translating, via the address translation service of the graphics processor unit, the guest physical address to a corresponding machine physical address.

17. The method of claim 16, wherein the graphics processor unit comprises one or more graphics virtualization registers;

wherein the hypervisor configures the one or more graphics virtualization registers to inform the graphics processor unit that one of the guest machines have been assigned to the graphics processor unit by the hypervisor; and

wherein the one or more graphics virtualization registers further identify where the lookup table is located for the assigned guest machine.

18. The method of claim 17, further comprising:

passing a Guest physical Frame Number (GFN) from the hypervisor to the graphics processor unit requesting translation of the GFN by the address translation service to a Machine Frame Number (MFN), wherein the GFN represents the guest physical address for one of the one or more guest machines and wherein the MFN represents the machine physical addresses within the main memory corresponding to the guest physical address specified by the access request.

19. The method of claim 16, wherein translating the guest physical address to a corresponding machine physical address comprises the address translation service of the graphics processor unit performing the translating based on a Guest physical Frame Number (GFN) to Machine Frame Number (MFN) mapping from the lookup table in the graphics memory.

20. The method of claim 19, wherein:

the address translation service retrieves the GFN to MFN mapping through a Translation Lookaside Buffer (TLB) integrated within the graphics processor unit; and

wherein the TLB provides an indexable cache on behalf of the address translation service of the graphics processor unit.

21. The method of claim 16, wherein the graphics processor unit comprises a graphics virtualization determination component;

determining, via the graphics virtualization determination component, whether or not the graphics processor unit is operating within a virtualization environment on behalf of one of the guest machines;

engaging the address translation service for guest physical addresses associated with the graphics processor unit operating within the virtualization environment; and

bypassing the address translation service for logical addresses which are not associated with the graphics processor unit operating within the virtualization environment, wherein the system to implement logical memory address to guest physical address translation without engaging the address translation service of the graphics processor unit to translate the logical addresses.

22. The method of claim 16, further comprising:

enabling virtualization in the graphics processor unit by communicating a configuration request from the hypervisor to the graphics processor unit;

preparing the lookup table internal to the hypervisor; and

wherein transferring the lookup table to the graphics memory of the graphics processor unit comprises the hypervisor transferring the prepared lookup table to the graphics processor unit.

23. The method of claim 22, wherein the hypervisor transferring the prepared lookup table to the graphics processor unit comprises the hypervisor writing the lookup table into shared graphics memory of the graphics processor unit.

24. The method of claim 22, wherein the hypervisor transferring the prepared lookup table to the graphics processor unit comprises:

the hypervisor instructing the graphics processor unit to retrieve and store the prepared lookup table;

the graphics processor unit responsively issuing a Direct Memory Access (DMA) request to fetch the prepared lookup table; and

the graphics processor unit responsively storing the lookup table in graphics memory internal to the graphics processor unit.

25. The method of claim 16, further comprising:

the hypervisor issuing a lookup table update to the graphics processor unit; and

the graphics processor unit responsively updating the lookup table in the graphics memory.

26. The method of claim 16, wherein the graphics processor unit comprises a microprocessor within a tablet computing device or a smart phone or one of a plurality of microprocessors integrated within the tablet computing device or the smartphone.

27. A graphics processor unit embodied within a silicon integrated circuit, the graphics processor unit comprising:

a shared graphics memory interface to receive a prepared lookup table from a hypervisor;

a graphics memory to store the prepared lookup table therein, wherein the prepared lookup table to store a Guest physical Frame Number (GFN) to Machine Frame Number (MFN) mapping;

an address translation service unit to receive a Guest physical Frame Number for translation; and

a Translation Lookaside Buffer (TLB) to retrieve a Machine Frame Number corresponding to the received Guest physical Frame Number from the prepared lookup table to fulfill the translation.

28. The graphics processor unit of claim 27:

wherein the graphics processor unit to perform address translation services on behalf of one or more guest machines operating within a tablet computing device or a smartphone;

wherein the tablet computing device or the smartphone comprises a separate and distinct central processing unit communicatively interfaced with the graphics processor unit within the tablet computing device or the smartphone; and

wherein the central processing unit lacks dedicated hardware circuitry to perform address translation of guest physical addresses to machine physical addresses.

29. The graphics processor unit of claim 27, further comprising:

one or more graphics virtualization registers;

wherein the one or more graphics virtualization registers inform the graphics processor unit that a guest machine has been assigned to the graphics processor unit by the hypervisor.

30. The graphics processor unit of claim 29, wherein the one or more graphics virtualization registers further identify where the lookup table is located for the assigned guest machine.

31. The graphics processor unit of claim 27, further comprising:

a graphics virtualization determination component integrated within the graphics processor unit;

wherein the graphics virtualization determination component is to determine whether or not the graphics processor unit is operating within a virtualization environment on behalf of one or more guest machines; and

wherein the graphics processor unit to engage the address translation service when operating within the virtualization environment.