Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

• US 20140355343A1
• Filed: 06/17/2014
• Published: 12/04/2014
• Est. Priority Date: 10/24/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 9,153,333 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 : Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Claims

1-22. -22. (canceled)

23. A method of operating a semiconductor storage device comprising a plurality of memory cells connected in series and each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer above said floating body for storing data as non-volatile memory, the method comprising:

transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating bodies, when power to the device is interrupted;

wherein if said volatile memory is in a first state, electrons are injected into said floating gate or trapping layer and if said memory cell is in a second state, no electron injection into said floating gate or trapping layer occurs.

24. The method of claim 23, further comprising initializing the floating gates or trapping layers, to each a predetermined state prior to the transferring, wherein each said predetermined state of each of the floating gates or trapping layers is the same.

25. The method of claim 23, wherein the data transferred is stored in the floating gates or trapping layers with charges that are complementary to charges of the floating bodies that stored the data.

26. The method of claim 23, wherein at least one of said memory cells is a selected cell and a remainder of said memory cells are passing cells;

wherein each said memory cell connected in series includes a control gate, said method further comprising applying a voltage to the control gates, wherein voltage applied to said control gates of said passing cells is greater than voltage applied to said control gate of said at least one selected cell.

27. The method of claim 23, wherein said memory cells connected in series are substantially planar.

28. The method of claim 23 wherein said memory cells connected in series comprise three-dimensional cells, each having a fin extending from a substrate.

29. A method of operating a semiconductor storage device comprising a plurality of memory cells connected in series and each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer above said floating body for storing data as non-volatile memory, the method comprising:

restoring power to said memory cells; and

transferring the data stored in the floating gates or trapping layers, by a parallel, non-algorithmic restore process, to the floating bodies corresponding to the floating gates or trapping layers, when power is restored to said memory cells.

30. The method of claim 29, further comprising initializing the floating bodies to a predetermined state prior to the transferring, wherein said predetermined state of each of said floating bodies is the same.

31. The method of claim 29, wherein the data transferred to the floating bodies are complementary to charges stored in the corresponding floating gates or trapping layers.

32. The method of claim 29, wherein at least one of said memory cells is a selected cell and a remainder of said memory cells are passing cells;

wherein each said memory cell connected in series includes a control gate, said method further comprising applying a voltage to the control gates, wherein voltage applied to said control gates of said passing cells is greater than voltage applied to said control gate of said at least one selected cell.

33. The method of claim 32, wherein said voltage applied to said control gate of at least one selected cell is a negative voltage.

34. The method of claim 29, wherein said memory cells connected in series are substantially planar.

35. The method of claim 29, wherein said memory cells connected in series comprise three-dimensional cells, each having a fin extending from a substrate.

36. A method of operating a semiconductor storage device comprising a plurality of memory cells connected in series and each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer above said floating body for storing data as non-volatile memory, the method comprising:

transferring the data stored in the floating gates or trapping layers, by a parallel, non-algorithmic restore process, to the floating bodies corresponding to the floating gates or trapping layers, when power is restored to the cell, and

restoring the floating gates or trapping layers to a predetermined charge state after the restore process.

37. The method of claim 36, further comprising initializing the floating bodies to each have a same predetermined state prior to the transferring.

38. The method of claim 36, wherein the data transferred to the floating bodies are complementary to charges stored in the corresponding floating gates or trapping layers.

39. The method of claim 36, wherein at least one of said memory cells is a selected cell and a remainder of said memory cells are passing cells;

wherein each said memory cell connected in series includes a control gate, said method further comprising applying a voltage to the control gates, wherein voltage applied to said control gates of said passing cells is greater than voltage applied to said control gate of said at least one selected cell.

40. The method of claim 39, wherein voltage applied to said control gate of said at least one selected cell is a negative voltage.

41. The method of claim 36, wherein said memory cells connected in series are substantially planar.

42. The method of claim 36, wherein said memory cells connected in series comprise three-dimensional cells, each having a fin extending from a substrate.