CONTINUOUS TUNING OF PREAMBLE RELEASE TIMING IN A DOUBLE DATA-RATE MEMORY DEVICE INTERFACE

• US 20140355359A1
• Filed: 05/31/2013
• Published: 12/04/2014
• Est. Priority Date: 05/31/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Linam, David, Evans, Scott T., Humphrey, Guy
• Granted Patent: US 9,190,129 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0041 Delay of data signal

Abstract

Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Claims

1. A method for preamble release training in a double data-rate memory device interface, comprising:

generating a first signal in response to an initiation of a read operation, the first signal delayed from the initiation of the read operation by one or more clock cycles plus a fine delay of less than one clock cycle provided by an adjustable delay circuit;

providing the first signal to a data strobe parking circuit;

generating a second signal in response to the initiation of the read operation, the second signal delayed by the adjustable delay circuit;

receiving a data strobe signal associated with incoming data during the read operation;

comparing an edge of the second signal with an edge of the data strobe signal associated with incoming data during the read operation; and

adjusting the adjustable delay circuit in response to a result of comparing the edge of the second signal with the edge of the data strobe signal.

2. The method of claim 1, wherein the adjustable delay circuit receives a delay input from a first delay register to generate the first signal and receives the delay input from a second delay register to generate the second signal.

3. The method of claim 2, wherein:

generating a first signal comprises generating the first signal in response to an output of a state machine; and

generating a second signal comprises generating the second signal in response to the output of the state machine.

4. The method of claim 3, wherein:

the state machine selects one of the first delay register and the second delay register to provide an output to the adjustable delay circuit; and

the state machine receives a most-significant bit of a selected one of the first delay register and the second delay register, and the adjustable delay circuit receives less-significant bits of the selected one of the first delay register and the second delay register.

5. The method of claim 3, wherein adjusting the adjustable delay comprises the state machine selecting one of incrementing and decrementing a first value stored in the first delay register and a second value stored in the second delay register.

6. The method of claim 5, further comprising adding a fine offset value to one of a first value stored in the first delay register and the second value stored in the second delay register.

7. The method of claim 2, wherein:

generating a first signal comprises generating a first pulse; and

generating a second signal comprises generating a second pulse.

8. A system for preamble release training in an interface between an application-specific integrated circuit (ASIC) and a double data-rate memory device, comprising:

an adjustable delay circuit;

an auto-tune circuit configured to generate a first signal and a second signal in response to an initiation of a read operation by the ASIC, the adjustable delay circuit delaying the first signal to produce a preamble release signal and delaying the second signal to produce an auto-tune clock signal;

a data strobe parking circuit having an input receiving a data strobe signal associated with incoming data during the read operation and having an output switchable between a data strobe signal and a fixed voltage, switching of the preamble release being controlled by the preamble release signal; and

a comparator circuit configured to compare an edge of the auto-tune clock signal with an edge of the data strobe signal associated with incoming data during the read operation, wherein the auto-tune circuit provides an adjustment signal to the adjustable delay in response to a result of comparing the edge of the second signal with the edge of the data strobe signal.

9. The system of claim 8, further comprising:

a multiplexer having an output providing the adjustment signal to the adjustable delay circuit, the multiplexer receiving a multiplexer control signal from the auto-tune circuit;

a first delay register having an output coupled to a first input of the multiplexer; and

a second delay register having an output coupled to a second input of the multiplexer.

10. The system of claim 9, wherein the first delay register and the second delay register are loadable by the ASIC.

11. The system of claim 9, wherein:

the auto-tune circuit comprises a state machine;

the adjustable delay circuit delays the first signal in response to a first output of the state machine produced when the state machine is in a first state; and

the adjustable delay delays the second signal in response to a second output of the state machine produced when the state machine is in a second state.

12. The system of claim 11, wherein:

the state machine generates the multiplexer control signal; and

the state machine receives a most-significant bit of a selected one of the first delay register and the second delay register, and the adjustable delay circuit receives all bits of the selected one of the first delay register and the second delay register except the most-significant bit.

13. The system of claim 12, wherein the state machine is responsive to a read enable signal provided by the ASIC.

14. The system of claim 13, further comprising delay adjustment logic, wherein the state machine produces an adjustment output signal, and the delay adjustment logic is configured to increment a first value stored in the first delay register and a second value stored in the second delay register when the adjustment output signal has a first state and decrement the first value stored in the first delay register and the second value stored in the second delay register when the adjustment output signal has a second state.

15. The system of claim 14, further comprising adder circuit configured to add a fine offset value to one of the first value stored in the first delay register and the second value stored in the second delay register.

16. The system of claim 8, wherein the comparator comprises a flip-flop having a clock input receiving the auto-tune clock signal and a data input receiving the data strobe signal.

17. The system of claim 8, wherein:

the auto-tune circuit comprises a state machine responsive to a read enable signal provided by the ASIC; and

the state machine is configured to transition states in response to a clock signal.

18. The system of claim 17, wherein the state machine includes a state transition responsive to two consecutive read operations occurring within a predetermined number of clock cycles of each other.

19. The system of claim 17, wherein the state machine is configured to generate the first signal and the second signal in response to a current state, the read enable signal, and a most-significant bit of a selected one of the first delay register and the second delay register.

20. The system of claim 19, wherein the adjustable delay circuit receives all bits of the selected one of the first delay register and the second delay register except the most-significant bit.

21. The system of claim 8, wherein the auto-tune circuit is configured to generate the first signal as a first pulse and to generate the second signal as a second pulse.