Memory Arbitrator for Electronics Communications Devices

• US 20140357191A1
• Filed: 08/18/2014
• Published: 12/04/2014
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: OCHIKUBO, Craig
• Granted Patent: US 9,280,499 B2
• Time in Patent Office: Days
• US Class Current: 455/41.1
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer
• CPC Class Codes: H04W 52/0261 managing power supply demand, e.g. depending on battery level
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Embodiments of the invention include electronic communications devices having a memory in near field communication device, a memory arbitrator and a host processor. The near field communication (NFC) devices are configured to receive data and drive power from the communication signal. The memory arbitrator is connected to the NFC device and the memory. The memory arbitrator is also configured to access the memory in response to an access request from the NFC device. Additionally, the memory is configurable to be accessed by both the host processor and the NFC device according to embodiments of the present invention.

Claims

1. A device, comprising:

a memory;

a communication device configured to receive a memory access request from a communication signal; and

a memory arbitrator coupled to the communication device and the memory and configured to;

determine a priority of the memory access request;

compare the determined priority of the memory access request to a priority associated with a current memory access; and

interrupt the current memory access upon a determination that the memory access request has a higher priority than the priority associated with the current memory access.

2. The device of claim 1, wherein the memory access request is associated with a component of the device.

3. The device of claim 2, wherein the memory arbitrator is further configured to grant access to the memory to the component of the device after interrupting the memory access of the device currently accessing the memory.

4. The device of claim 3, wherein the memory arbitrator is configured to grant access independently of a host processor.

5. The device of claim 1, wherein the memory arbitrator is further configured to determine a priority of a second memory request.

6. The device of claim 5, wherein the memory arbitrator is further configured to:

compare the priority of the second memory request to a priority associated with a second current memory access; and

allow the second current memory access to continue without interruption upon determining that the second memory request has a lower priority than the priority associated with the second current memory access.

7. The device of claim 1, wherein the communication device comprises a near field communication (NFC) device configured to receive data, power, and the memory access request from the communication signal.

8. The device of claim 1, wherein the memory arbitrator is configured to be powered by power derived by the NFC device.

9. The device of claim 7, wherein the memory arbitrator is configured to perform power management functions.

10. The device of claim 9, wherein the power management functions comprise activating one or more components of the device.

17. The method of claim 1, further comprising:

receiving the memory access request from a communication signal.

18. The method of claim 17, further comprising:

receiving data and power from the communication signal.

19. The method of claim 18, further comprising:

powering one or more components of the device with the power received from the communication signal.

11. A method of managing memory access in a device, comprising:

determining a priority of a memory access request;

comparing the determined priority of the memory access request to a priority associated with a current memory access; and

interrupting the current memory access upon determining that the memory access request has a higher priority than the priority associated with the current memory access.

12. The method of claim 11, wherein the memory access request is associated with a component of the device.

13. The method of claim 12, further comprising:

granting access to the component of the device after interrupting the memory access of the device currently accessing the memory.

14. The method of claim 13, wherein granting access comprises granting access independently of a host processor.

15. The method of claim 11, further comprising:

determining a priority of a second memory access request.

16. The method of claim 15, further comprising:

comparing the priority of the second memory access request to a priority associated with a second current memory access; and

allowing the second current memory access continue without interruption upon determining that the second memory access request has a lower priority than the priority associated with the second current memory access.

20. The method of claim 11, further comprising activating one or more components of the device.