Graphical Development and Deployment of Parallel Floating-Point Math Functionality on a System with Heterogeneous Hardware Components

• US 20140359589A1
• Filed: 10/25/2013
• Published: 12/04/2014
• Est. Priority Date: 05/30/2013
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Andrade, Hugo A., Odom, Brian Keith, Butler, Cary Paul, MacCleery, Brian C., Nagle, James C., Monroe, J. Marcus, Barp, Alexandre M.
• Granted Patent: US 9,235,395 B2
• Time in Patent Office: Days
• US Class Current: 717/149
• CPC Class Codes: G06F 2207/48 Indexing scheme relating to groups G06F7/48 - G06F7/575
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 8/34 Graphical or visual programming
• CPC Class Codes: G06F 8/451 Code distribution considering CPU load at run-time G06F9/505; load rebalancing G06F9/5083

Abstract

System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Claims

1. A non-transitory computer accessible memory medium that stores program instructions for configuring a system of heterogeneous hardware components, wherein the program instructions are executable by a processor to:

create a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware element, at least one digital signal processor (DSP) core, and at least one programmable communication element (PCE);

automatically determine respective portions of the graphical program for deployment to respective ones of the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions;

automatically generate first program code implementing communication functionality between the at least one programmable hardware element and the at least one DSP core, wherein the first program code is targeted for deployment to the at least one programmable communication element; and

automatically generate at least one hardware configuration program from the graphical program and the first program code, wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program code for deployment to respective ones of the heterogeneous hardware components;

wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured to execute the graphical program concurrently, including the floating point math functionality.

2. The non-transitory computer accessible memory medium of claim 1, wherein the system comprises a heterogeneous system on a chip.

3. The non-transitory computer accessible memory medium of claim 1, wherein the system comprises a heterogeneous system implemented on multiple chips.

4. The non-transitory computer accessible memory medium of claim 1, wherein the program instructions are further executable to:

automatically deploy the hardware configuration program to the system.

5. The non-transitory computer accessible memory medium of claim 1, wherein the heterogeneous hardware components further include at least one microprocessor.

6. The non-transitory computer accessible memory medium of claim 1, wherein the heterogeneous hardware components further include at least one at least one graphics processing unit (GPU).

7. The non-transitory computer accessible memory medium of claim 1, wherein the at least one PCE comprises one or more PCEs for internal communications between the at least one programmable hardware element and the at least one DSP core.

8. The non-transitory computer accessible memory medium of claim 1, wherein the at least one PCE comprises at least one I/O block for communications between the at least one programmable hardware element or the at least one DSP core and external components or systems.

9. The non-transitory computer accessible memory medium of claim 1, wherein the system comprises one or more chips, and wherein the at least one PCE is configurable for intra-chip communications or inter-chip communications.

10. The non-transitory computer accessible memory medium of claim 1, wherein to create the graphical program, the program instructions are executable to:

generate the graphical program based on one or more of;

at least one text-based program;

at least one simulation or model;

at least one circuit diagram;

at last one network diagram;

or

at least one statechart.

11. The non-transitory computer accessible memory medium of claim 1, wherein the graphical program comprises a graphical data flow program.

12. The non-transitory computer accessible memory medium of claim 1, wherein the graphical program comprises a plurality of graphical data transfer and synchronization mechanisms represented by graphical floating-point programming nodes, functions, and wires, wherein the graphical data transfer and synchronization mechanisms are deployable to the heterogeneous hardware components, thereby enabling the heterogeneous hardware components implementing the floating-point math functionality to simulate physical systems in which measurements, state-values, inputs, outputs and parameters are shared between the heterogeneous hardware components.

13. The non-transitory computer accessible memory medium of claim 1, wherein the graphical program comprises multiple models of computation.

14. A method for configuring a system of heterogeneous hardware components, the method comprising:

creating a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware element, at least one digital signal processor (DSP) core, and at least one programmable communication element (PCE);

automatically determining respective portions of the graphical program for deployment to respective ones of the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions;

automatically generating first program code implementing communication functionality between the at least one programmable hardware element and the at least one DSP core, wherein the first program code is targeted for deployment to the at least one programmable communication element; and

automatically generating at least one hardware configuration program from the graphical program and the first program code, wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program code for deployment to respective ones of the heterogeneous hardware components;

wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured to execute the graphical program concurrently, including the floating point math functionality.

15. The method of claim 14, wherein the system comprises a heterogeneous system on a chip.

16. The method of claim 14, wherein the system comprises a heterogeneous system implemented on multiple chips.

17. A non-transitory computer accessible memory medium that stores program instructions for configuring a system of heterogeneous hardware components, wherein the program instructions are executable by a processor to:

create a graphical program that includes floating point functionality, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including;

at least one programmable hardware element;

at least one digital signal processor (DSP) core;

at least one programmable communication element (PCE);

automatically determining respective portions of the graphical program for respective deployment to the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions, wherein the respective portions comprise;

a first portion targeted for deployment to the at least one programmable hardware element; and

a second portion targeted for deployment to the at least one DSP core;

automatically generating program code implementing communication functionality between the at least one programmable hardware element and the at least one DSP core, using the at least one communication element;

automatically generating at least one hardware configuration program from the graphical program, including;

compiling the first portion of the graphical program for deployment to the at least one programmable hardware element, thereby generating a first portion of the at least one hardware configuration program;

compiling the second portion of the graphical program for deployment to the at least one DSP core, thereby generating a second portion of the at least one hardware configuration program;

compiling the automatically generated program code implementing communication functionality for deployment to the at least one communication element, thereby generating a third portion of the at least one hardware configuration program;

wherein the hardware configuration program is deployable to the system, including;

configuring the at least one programmable hardware element with the first portion of the at least one hardware configuration program;

configuring the at least one DSP core with the second portion of the at least one hardware configuration program; and

configuring the at least one communication element with the third portion of the at least one hardware configuration program;

wherein after deployment, the system is configured to execute the graphical program concurrently, including the floating point functionality, wherein during execution;

the at least one programmable hardware element performs the functionality of the first portion of the graphical program;

the at least one DSP core performs the functionality of the second portion of the graphical program; and

the at least one communication element implements communication between the at least one programmable hardware element and the at least one DSP core.

18. The non-transitory computer accessible memory medium of claim 17, wherein the system comprises a heterogeneous system on a chip.

19. The non-transitory computer accessible memory medium of claim 17, wherein the system comprises a heterogeneous system implemented on multiple chips.

20. The non-transitory computer accessible memory medium of claim 17, wherein the graphical program comprises a graphical data flow program.