THREE DIMENSIONAL MEMORY ARRAY WITH SELECT DEVICE

• US 20140361239A1
• Filed: 06/11/2013
• Published: 12/11/2014
• Est. Priority Date: 06/11/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ramaswamy, D.V. Nirmal, Sills, Scott E., Sandhu, Gurtej S.
• Granted Patent: US 9,728,584 B2
• Time in Patent Office: Days
• US Class Current: 257/5
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

Claims

1. A three dimensional memory array, comprising:

a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material;

at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects each of the plurality of first conductive lines;

storage element material arranged around the at least one conductive extension; and

a select device arranged around the storage element material,

wherein the storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

2. The memory array of claim 1, wherein the select device arranged around the storage element material includes:

an inner concentric conductor material; and

an outer concentric non-metallic material arranged around the inner concentric conductor material.

3. The memory array of claim 2, wherein the outer concentric non-metallic material includes a semiconductor material.

4. The memory array of claim 2, wherein the outer concentric non-metallic material includes an insulator material.

5. The memory array of claim 2, wherein the outer concentric non-metallic material includes a lamellar stack that includes alternating semiconductor and insulator materials.

6. The memory array of claim 2, wherein the outer concentric non-metallic material includes a non-metallic conductor that behaves as a non-ohmic device.

7. The memory array of claim 2, wherein the plurality of first conductive lines and inner concentric conductor material include a same metal material, and the outer concentric non-metallic material includes silicon.

8. The memory array of claim 2, wherein the plurality of first conductive lines and inner concentric conductor material include titanium nitride (TiN).

9. The memory array of claim 1, wherein the select device is a metal-insulator-metal select device.

10. The memory array of claim 1, wherein the select device is a metal-semiconductor-metal select device.

11. The memory array of claim 1, wherein the select device is an ovonic threshold switch.

12. The memory array of claim 1, further comprising buffer material arranged around the storage element material, the buffer material being located between the select device and the storage element material.

13. A three dimensional memory array, comprising:

a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material;

at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines;

buffer material, storage element material, conductor material, and semiconductor material arranged around the at least one conductive extension,

wherein a first instance of the conductor material is adjacent a first instance of the semiconductor material, and the first instances of the conductor material and the semiconductor material are isolated from second instances of the conductor material and the semiconductor material, and

wherein the at least one conductive extension, buffer material, and storage element material are contiguous between the first and second instances of the conductor material and the semiconductor material.

14. The memory array of claim 13, wherein the buffer material, storage element material, conductor material, and semiconductor material is concentrically arranged around the at least one conductive extension

15. The memory array of claim 13, wherein the conductor material is arranged between the semiconductor material and the at least one conductive extension.

16. The memory array of claim 13, wherein the first instances of the conductor material and the semiconductor material are isolated from the second instances of the conductor material and the semiconductor material by at least the insulation material separating the plurality of first conductive lines.

17. The memory array of claim 13, wherein the buffer material is arranged between the storage element material and the at least one conductive extension.

18. The memory array of claim 13, further comprising a plurality of second conductive lines arranged to extend substantially perpendicular to the plurality of first conductive lines at different levels than levels at which the plurality of first conductive lines are arranged, and arranged to extend substantially perpendicular to the at least one conductive extension,

wherein the at least one conductive extension is coupled to at least one of the plurality of second conductive lines.

19. The memory array of claim 18, further comprising second buffer material arranged to extend substantially perpendicular to and along each of two edges of the plurality of first conductive lines at different levels than the levels at which the plurality of first conductive lines are arranged, and arranged to extend substantially perpendicular to the at least one conductive extension,

wherein the second buffer material is coupled to the buffer material.

20. The memory array of claim 18, further comprising second storage element material arranged to extend substantially perpendicular to and along each of two edges of the second buffer material at different levels than the levels at which the plurality of first conductive lines are arranged, and arranged to extend substantially perpendicular to the at least one conductive extension,

wherein the second storage element material is coupled to the storage element material.

21. A three dimensional memory array, comprising:

a stack of alternating levels of conductive lines and insulation material;

a conductive extension arranged to extend substantially perpendicular to the conductive lines, such that the conductive extension intersects each of the conductive lines;

storage element material concentrically arranged around a length of the conductive extension, the storage element material being contiguous along the length of the conductive extension; and

a plurality of discrete select devices, the plurality of discrete select devices each having a ring geometry, a respective one of the plurality of discrete select devices being located adjacent a respective conductive line, and each of the plurality of discrete select devices,

wherein each of the plurality of discrete select devices includes a non-metallic material at an outside diameter of the ring geometry and a conductor material at an inside diameter of the ring geometry.

22. The memory array of claim 21, wherein the conductive lines and the conductor material at the inside diameter of the ring geometry comprise a same metal material.

23. The memory array of claim 21, wherein the non-metallic material at the outside diameter of the ring geometry comprises a semiconductor material.

24. The memory array of claim 21, wherein the non-metallic material at the outside diameter of the ring geometry comprises a dielectric material.

25. A method of forming a three dimensional memory array, comprising:

forming a stack comprising a plurality of first conductive lines separated from one another by insulation material;

forming a via through the stack such that at least a portion of the via passes through each of the plurality of first conductive lines;

forming a recess in at least one of the plurality of first conductive lines adjacent the via;

forming a select device in the recess;

forming storage element material within the via; and

forming a conductive extension within the via.

26. The method of claim 25, further comprising forming a buffer material in the via adjacent the storage element material and the conductive extension.

27. The method of claim 25, wherein forming a select device in the recess includes:

forming non-metallic material in the recess; and

forming conductor material in the recess.

28. The method of claim 27, wherein forming the conductor material in the recess includes forming the conductor material of a same material as the plurality of first conductive lines.

29. The method of claim 27, wherein forming a select device in the recess includes:

first forming the non-metallic material in the recess; and

subsequently forming the conductor material in the recess.

30. The method of claim 27, wherein forming the non-metallic material in the recess includes:

depositing a semiconductor material in the recess; and

removing only a portion of the semiconductor material in the recess to form a second recess.

31. The method of claim 30, wherein depositing the semiconductor material in the recess includes conformally depositing the semiconductor material in the via and recess by a chemical vapor deposition (CVD) method when the plurality of first conductive lines includes less than six (6) first conductive lines and the via has an aspect ratio of less than six-to-one (6:

1).

32. The method of claim 30, wherein depositing the semiconductor material in the recess includes conformally depositing the semiconductor material in the via and recess by an atomic layer deposition (ALD) method when the plurality of first conductive lines includes between fourteen (14) and nineteen (19) inclusive, and the via has an aspect ratio of between nine-to-one (9:

1) and eleven-to-one (11;

1).

33. The method of claim 30, wherein forming the conductor material in the recess includes forming the conductor material in the second recess.

34. The method of claim 27, wherein forming the recess includes forming the recess at an exposed region of each of the first conductive lines in a wall of the via by a non-directional etch that is more selective to the first conductive lines than the insulation material;

and

wherein forming the conductor material in the recess includes;

depositing the conductor material within the recess, and

removing the conductor material not within the recess.

35. The method of claim 25, further comprising forming a plurality of second conductive lines arranged to extend substantially perpendicular to the plurality of first conductive lines at a different level than a number of levels at which the plurality of first conductive lines are arranged, and arranged to extend substantially perpendicular to the conductive extension,

wherein the conductive extension is coupled to at least one of the plurality of second conductive lines.

36. The method of claim 35, wherein forming the plurality of second conductive lines includes forming the plurality of second conductive lines by a dual-damascene process.

37. A method of forming a memory array, comprising:

forming a stack comprising a number of first conductive lines separated from one another by insulation material;

forming a via through the stack such that at least a portion of the via passes through each of the number of first conductive lines;

forming a recess in at least one of the number of first conductive lines adjacent the via;

forming a select device in the recess in the number of first conductive lines adjacent the via;

forming storage element material within the via adjacent the select device; and

forming a conductive extension concentrically within the storage element material.

38. The method of claim 37, wherein forming the select device in the recess includes forming one of a metal-semiconductor-metal device and a metal-insulator-metal device with one of the number of first conductive lines.

39. The method of claim 37, wherein forming the via includes forming the via to have a particular aspect ratio, and forming the select device includes depositing material comprising the select device in the recess,

wherein the particular aspect ratio of the via and the process by which the material comprising the select device is deposited in the recess is based on current density of the select device.