SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

• US 20140362267A1
• Filed: 08/25/2014
• Published: 12/11/2014
• Est. Priority Date: 07/05/2011
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kagawa, Yoshihisa, Aoyagi, Kenichi, Hagimoto, Yoshiya, Fujii, Nobutoshi
• Granted Patent: US 9,111,763 B2
• Time in Patent Office: Days
• US Class Current: 348/302
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2224/02245 Flow barrier
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05578 being disposed next to each other, e.g. side-to-side arrangements
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05686 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/08058 : being non uniform along the bonding area
• CPC Class Codes: H01L 2224/08121 : the connected bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/08501 : at the bonding interface
• CPC Class Codes: H01L 2224/0903 : Bonding areas having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/09517 : including bonding areas providing primarily mechanical support
• CPC Class Codes: H01L 2224/80011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/80013 : Plasma cleaning
• CPC Class Codes: H01L 2224/80035 : by heating means
• CPC Class Codes: H01L 2224/80091 : Under pressure
• CPC Class Codes: H01L 2224/80097 : Heating
• CPC Class Codes: H01L 2224/80203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/8034 : Bonding interfaces of the bonding area
• CPC Class Codes: H01L 2224/80345 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/80357 : being flush with the surface
• CPC Class Codes: H01L 2224/80359 : Material
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80935 : by heating means, e.g. reflowing
• CPC Class Codes: H01L 2224/80986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/83345 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/53223 : Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 : Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/564 : Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/14609 : Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14625 : Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 27/1464 : Back illuminated imager structures
• CPC Class Codes: H01L 27/14645 : Colour imagers
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/049 : Nitrides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/053 : Oxides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H04N 25/70 : SSIS architectures; Circuits associated therewith

Abstract

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

Claims

1. A semiconductor device, comprising:

a first substrate having a bonding face to which a first electrode and a first insulating film are exposed;

an insulating thin film configured to cover the bonding face of said first substrate; and

a second substrate having a bonding face to which a second electrode and a second insulating film are exposed and bonded to said first substrate in a state in which said insulating thin film is sandwiched between the bonding face of said second substrate and the bonding face of said first substrate and said first electrode and said second electrode are electrically connected to each other through said insulating thin film.

2. The semiconductor device according to claim 1, wherein said insulating thin film is an oxide film.

3. The semiconductor device according to claim 1, wherein said insulating thin film is a nitride film.

4. The semiconductor device according to claim 1, wherein said insulating thin film has a lamination structure.

5. The semiconductor device according to claim 1, wherein said insulating thin film is provided in a state in which said insulating thin film covers an overall area of each of the bonding faces.

6. The semiconductor device according to claim 1, wherein the bonding face of said first substrate and the bonding face of said second substrate are flattened faces.

7. A fabrication method for a semiconductor device, comprising:

preparing two substrates each having a bonding face to which an electrode and an insulating film are exposed;

forming an insulating thin film in a state in which the insulating thin film covers the bonding face of at least one of the two substrates; and

disposing the two substrates such that the bonding faces thereof are opposed to each other across the insulating thin film, positioning the two substrates in a state in which the electrodes thereof are electrically connected to each other through the insulating thin film and bonding the two substrates in the positioned state.

8. The fabrication method for a semiconductor device according to claim 7, wherein the insulating thin film is formed on both of the two substrates.

9. The fabrication method for a semiconductor device according to claim 7, wherein the insulating thin film of a same material is formed on both of the two substrates.

10. The fabrication method for a semiconductor device according to claim 7, wherein the insulating thin film is formed by an atomic layer deposition method.

11. The fabrication method for a semiconductor device according to claim 7, wherein the bonding faces of the two substrates are formed by a flattening process.

12. A camera system comprising:

a solid-state image pickup device;

an optical system that forms a subject image on the solid-state imaging device; and

a signal processing circuit that processes an output image signal of the solid-state imaging device, wherein the solid-state image pickup device includes;

a first substrate having a bonding face to which a first electrode and a first insulating film are exposed;

an insulating thin film configured to cover the bonding face of said first substrate; and

a second substrate having a bonding face to which a second electrode and a second insulating film are exposed and bonded to said first substrate in a state in which said insulating thin film is sandwiched between the bonding face of said second substrate and the bonding face of said first substrate and said first electrode and said second electrode are electrically connected to each other through said insulating thin film.

13. The camera system according to claim 12, wherein said insulating thin film is an oxide film.

14. The camera system according to claim 12, wherein said insulating thin film is a nitride film.

15. The camera system according to claim 12, wherein said insulating thin film has a lamination structure.

16. The camera system according to claim 12, wherein said insulating thin film is provided in a state in which said insulating thin film covers an overall area of each of the bonding faces.

17. The camera system according to claim 12, wherein the bonding face of said first substrate and the bonding face of said second substrate are flattened faces.