LATCH-UP FREE VERTICAL TVS DIODE ARRAY STRUCTURE USING TRENCH ISOLATION

• US 20140363930A1
• Filed: 06/08/2013
• Published: 12/11/2014
• Est. Priority Date: 11/30/2006
• Status: Active Grant

• Current Assignee: Madhur Bobde
• Original Assignee: Madhur Bobde
• Inventors: Bobde, Madhur
• Granted Patent: US 9,202,938 B2
• Time in Patent Office: Days
• US Class Current: 438/133
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0744 without components of the field effect type
• CPC Class Codes: H01L 27/075 Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
• CPC Class Codes: H01L 27/0755 Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0761 Vertical bipolar transistor in combination with diodes only
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/7416 the device being an antiparallel diode, e.g. RCT shorted anode structures enabling reverse conduction H01L29/0834
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/866 Zener diodes

Abstract

A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

Claims

1. A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device, the method comprising:

opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate to form a first, second, third fourth and fifth semiconductor regions separated by said isolation trenches followed by applying a body mask for doping a body region having a second conductivity type in an upper part of said epitaxial layer with the body region extends laterally over an entire length of the semiconductor regions between two of the isolation trenches;

applying an source mask for implanting a plurality of doped regions of said first conductivity type in each of the semiconductor regions including a top doped region of the first conductivity type disposed under a top surface of the substrate encompassed in said body region and extends laterally over substantially an entire length of the first semiconductor region to constitute a bipolar transistor comprising two vertically stacked PN junctions disposed between the isolation trenches for triggering the bipolar transistor by a Zener diode comprising a bottom vertically stacked PN junction between the body region and the epitaxial layer for carrying a transient current for suppressing a transient voltage;

the step of implanting the doped region of the first conductivity type further implanting dopant regions of the first conductivity type interfacing with the body region as low side diodes in the second and third semiconductor regions to work with the Zener diode as part of the TVS array; and

the step of implanting the doped region of the first conductivity type further implanting dopant regions of the first conductivity type in the fourth and fifth semiconductor regions to interface with the body region

2. The method of claim 1 further comprising:

forming a first I/O pad by depositing and patterning a metal layer on top of the semiconductor substrate to electrically connect the first high side and first low side diodes and forming a second I/O pad by depositing and patterning the metal layer on top of the semiconductor substrate to electrically connect the second high side and second low side diodes.

3. The method of claim 1 further comprising:

applying a contact mask for implanting doped regions of the second conductivity type away from the body region for constituting the first and second high side diodes with said epitaxial layer to connect to said low side diodes encompassed in said body region with the first and second input-output (IO) contact pads across said isolation trenches.

4. The method of claim 1 wherein:

said step implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes in said step further comprising a step of forming a Zener doped region with a greater width wherein said Zener doped region comprising vertically stacked PN junctions in the first semiconductor region for functioning as a Zener diode with said body region in said epitaxial layer.

5. The method of claim 1 wherein:

said step opening a plurality of isolation trenches further comprising a step of opening isolation trenches or the first semiconductor region immediately next to said Zener diode for isolating said Zener diode for preventing said latch-up between said doped regions of different conductivity types.

6. The method of claim 1 further comprising:

depositing and patterning a metal layer on a bottom surface of said substrate to function as an electrode for said TVS array.

7. The method of claim 1 further comprising:

depositing a metal layer on a to surface of said substrate and patterning said metal layer to function as a cathode electrically connected one of the