ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DISPLAY INCLUDING THE SAME

• US 20140367658A1
• Filed: 04/29/2014
• Published: 12/18/2014
• Est. Priority Date: 06/17/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KWAK, WON KYU
• Granted Patent: US 9,472,507 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 2102/311 Flexible OLED
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

An array substrate includes a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer and/or on the second insulating layer. In addition, the wiring patterns are separated from each other, and extend toward a side of the substrate. The array substrate further includes a recess pattern disposed adjacent the wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of a top surface of the substrate, and an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.

Claims

1. An array substrate comprising:

a substrate;

a barrier layer disposed on the substrate;

a buffer layer disposed on the barrier layer;

a first insulating layer disposed on the buffer layer;

a second insulating layer disposed on the first insulating layer;

a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer and/or on the second insulating layer, and wherein the wiring patterns are separated from each other, and extend toward a side of the substrate,

a recess pattern disposed adjacent to the wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of the top surface of the substrate; and

an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.

2. The array substrate of claim 1, wherein a bottom surface of the recess pattern comprises the top surface of the substrate, and sidewalls of the recess pattern comprise inner side surfaces of the first insulating layer, the second insulating layer, the buffer layer and the barrier layer.

3. The array substrate of claim 1, wherein the recess pattern is provided in a plurality, and the recess patterns are disposed between the wiring patterns.

4. The array substrate of claim 3, wherein each of the wiring patterns comprises:

a wiring line interposed between the first insulating layer and the second insulating layer and extending toward the side of the substrate;

a wiring pad disposed on the second insulating layer, wherein the wiring pad has an end overlapping at least part of the wiring line, and has another end wider than the wiring line; and

a wiring connection portion in which the wiring line and the wiring pad contact each other and are electrically connected to each other.

5. The array substrate of claim 4, wherein the recess pattern is disposed between adjacent wiring lines and extends to between adjacent wiring pads.

6. The array substrate of claim 5, wherein a width of the recess pattern disposed between the wiring lines is greater than a width of the recess pattern disposed between the wiring pads.

7. The array substrate of claim 4, wherein the wiring line extends in a zigzag shape, and wherein at least one of the recess patterns is disposed between adjacent wiring lines.

8. The array substrate of claim 7, wherein the recess patterns are disposed between a plurality of wiring lines and are arranged in a matrix of a plurality of columns and a plurality of rows.

9. The array substrate of claim 4, further comprising a recess groove disposed inside the wiring pad and penetrating through the wiring pad, the second insulating layer, the first insulating layer, the buffer layer and the barrier layer to expose the top surface of the substrate.

10. The array substrate of claim 4, wherein the recess pattern is disposed outside an outermost wiring line among the wiring lines.

11. The array substrate of claim 10, further comprising a cell ID pattern disposed outside the outermost wiring line among the wiring lines, wherein the recess pattern is disposed along an outer circumference of the cell ID pattern.

12. The array substrate of claim 1, further comprising at least one cutting line which traverses at least part of the substrate and is defined on the substrate, and wherein the recess pattern is disposed adjacent to the cutting line.

13. The array substrate of claim 1, wherein the buffer layer comprises at least one material selected from the group consisting of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

14. The array substrate of claim 1, wherein the substrate is a flexible substrate.

15. The array substrate of claim 1, wherein the substrate comprises a base layer and a protective layer disposed on the base layer, and wherein the buffer layer is disposed on the protective layer.

16. The array substrate of claim 15, wherein the base layer comprises polyimide, and the protective layer comprises polyethylene terephthalate or polyethylene naphthalate.

17. The array substrate of claim 1, wherein the organic insulating layer covers the portion of the top surface of the substrate which is exposed by the recess pattern.

18. An array substrate having a display area and a non-display area which is located outside the display area, wherein the non-display area comprises:

a substrate;

a barrier layer which is disposed on the substrate;

a buffer layer which is disposed on the barrier layer;

a first insulating layer which is disposed on the buffer layer;

a second insulating layer which is disposed on the first insulating layer;

a plurality of wiring patterns which are disposed between the first insulating layer and the second insulating layer or on the second insulating layer, are separated from each other, and extend toward a side of the substrate;

a recess pattern which is disposed adjacent to the wiring patterns and is recessed from a top surface of the second insulating layer by a predetermined depth to expose at least part of the top surface of the substrate; and

an organic insulating layer which is disposed on the second insulating layer and exposes at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.

19. The array substrate of claim 18, wherein a bottom surface of the recess pattern comprises the top surface of the substrate, and sidewalls of the recess pattern comprise inner side surfaces of the first insulating layer, the second insulating layer, the buffer layer and the barrier layer.

20. The array substrate of claim 18, wherein the recess pattern is provided in a plurality, and the recess patterns are disposed between the wiring patterns.

21. The array substrate of claim 20, wherein each of the wiring patterns comprises:

a wiring line interposed between the first insulating layer and the second insulating layer and extends toward the side of the substrate;

a wiring pad on the second insulating layer, has an end overlapping at least part of the wiring line, and has the other end wider than the wiring line; and

a wiring connection portion in which the wiring line and the wiring pad contact each other and are electrically connected to each other.

22. The array substrate of claim 21, wherein the recess pattern is disposed between adjacent wiring lines and extends to between adjacent wiring pads.

23. The array substrate of claim 22, wherein a width of the recess pattern disposed between the wiring lines is greater than a width of the recess pattern disposed between the wiring pads.

24. The array substrate of claim 21, wherein the wiring line extends in a zigzag shape, and one or more recess patterns are disposed between adjacent wiring lines.

25. The array substrate of claim 24, wherein the recess patterns are disposed between a plurality of wiring lines and are arranged in a matrix of a plurality of columns and a plurality of rows.

26. The array substrate of claim 21, further comprising a recess groove disposed inside the wiring pad and penetrates through the wiring pad, the second insulating layer, the first insulating layer, the buffer layer and the barrier layer to expose the top surface of the substrate.

27. The array substrate of claim 21, wherein the recess pattern is disposed outside an outermost wiring line among the wiring lines.

28. The array substrate of claim 21, further comprising a cell ID pattern disposed outside the outermost wiring line among the wiring lines, wherein the recess pattern is disposed along an outer circumference of the cell ID pattern.

29. The array substrate of claim 18, wherein at least one cutting line which traverses at least part of the substrate is defined on the substrate, and wherein the recess pattern is disposed adjacent to the cutting line.

30. The array substrate of claim 18, wherein the buffer layer comprises one selected from the group consisting of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

31. The array substrate of claim 18, wherein the wiring patterns comprise at least one of a plurality of gate wirings and a plurality of data wirings.

32. The array substrate of claim 18, wherein the substrate is a flexible substrate.

33. The array substrate of claim 18, wherein the substrate comprises a base layer and a protective layer disposed on the base layer, wherein the buffer layer is disposed on the protective layer.

34. The array substrate of claim 33, wherein the base layer is formed of polyimide, and the protective layer is formed of polyethylene terephthalate or polyethylene naphthalate.

35. The array substrate of claim 18, wherein the organic insulating layer covers the portion of the top surface of the substrate which is exposed by the recess pattern.

36. The array substrate of claim 18, wherein the wiring patterns comprise a plurality of gate wirings and a plurality of data wiring, wherein the gate wirings each comprise a gate pad, a gate electrode and a gate line disposed in the display area, and wherein the data wirings, each comprise a data pad, a source/drain electrode and a data line disposed in the display area, and wherein the wiring patterns further include wiring elements disposed in the non-display area which are formed of the same material as the gate wirings or the data wirings.

39. The array substrate of claim 18, wherein the organic insulating layer disposed on the second insulating layer covers sidewalls of the recess pattern and a bottom surface of the recess pattern.

37. An organic light-emitting display (OLED) comprising:

an array substrate comprising a display area and a non-display area located outside the display area; and

an encapsulation member disposed on the array substrate,

wherein the non-display area of the array substrate comprises;

a substrate,

a barrier layer disposed on the substrate,

a buffer layer disposed on the barrier layer,

a first insulating layer disposed on the buffer layer,

a second insulating layer disposed on the first insulating layer,

a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer and/or on the second insulating layer, and wherein the wiring patterns are separated from each other, and extend toward a side of the substrate,

a recess pattern disposed adjacent to the wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of the top surface of the substrate, and

an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.

38. The OLED of claim 37, wherein the encapsulation member is an encapsulation substrate or an encapsulation layer.

40. An organic light-emitting display (OLED) comprising:

an array substrate comprising a display area, and a non-display area disposed outside the display area; and

an encapsulation member disposed on the array substrate,

wherein the display area comprises;

a display area substrate,

a display area barrier layer disposed on the display area substrate,

a display area buffer layer disposed on the display area barrier layer,

a semiconductor layer disposed on the display area buffer layer,

a gate insulating layer disposed on the semiconductor layer,

a gate wiring including a gate line, a gate electrode and a gate pad disposed on the gate insulating layer,

an interlayer insulating film covering the gate wiring,

a data wiring including a source electrode, a drain electrode, and a data line disposed on the interlayer insulating film,

a planarization layer disposed on the data wiring and the interlayer insulating film,

a first electrode disposed on the planarization layer and electrically connected to the drain electrode,

a pixel defining layer disposed on the first electrode and exposing a portion of the first electrode,

an organic layer disposed on the portion of the first electrode exposed by the pixel defining layer, and

a second electrode disposed on the organic layer and the pixel defining layer, and

wherein the non-display area comprises;

a non-display area substrate,

a non-display area barrier layer disposed on the non-display area substrate,

a non-display area buffer layer disposed on the non-display area barrier layer,

a first insulating layer disposed on the non-display area buffer layer,

a second insulating layer disposed on the first insulating layer,

a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer and/or on the second insulating layer, and wherein the wiring patterns are separated from each other, and extend toward a side of the non-display area substrate;

a recess pattern disposed adjacent to the wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of the top surface of the non-display area substrate, and

an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the non-display area substrate which is exposed by the recess pattern.