SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

• US 20140367677A1
• Filed: 01/24/2013
• Published: 12/18/2014
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Miyamoto, Tadayoshi, Ito, Kazuatsu, Mori, Shigeyasu, Miyamoto, Mitsunobu, Ogawa, Yasuyuki, Nakazawa, Makoto, Matsuo, Takuya, Uchida, Seiichi
• Granted Patent: US 9,214,533 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: G02F 2201/50 Protective arrangements
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.

Claims

1. A semiconductor device comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating layer formed over the gate electrode;

an oxide semiconductor layer formed on the gate insulating layer;

source and drain electrodes electrically connected to the oxide semiconductor layer;

a first transparent electrode electrically connected to the drain electrode;

an interlayer insulating layer including a dielectric layer which has been formed over the source and drain electrodes; and

a second transparent electrode which has been formed on the interlayer insulating layer,

wherein at least a portion of the second transparent electrode overlaps with the first transparent electrode with the dielectric layer interposed between them, and

the oxide semiconductor layer and the first transparent electrode are formed out of the same oxide film.

2. The semiconductor device of claim 1, wherein the drain electrode is formed on the first transparent electrode, and

the first transparent electrode contacts directly with the drain electrode.

3. The semiconductor device of claim 1, further comprising an insulating protective layer formed on the source and drain electrodes,

wherein the insulating protective layer is formed to contact with a channel region of the oxide semiconductor layer, and

the insulating protective layer is made of an oxide.

4. The semiconductor device of claim 1, wherein at least one of the gate insulating layer and the dielectric layer includes an oxide insulating layer, and

the oxide insulating layer contacts with the oxide semiconductor layer.

5. The semiconductor device of claim 1, wherein the oxide film includes In, Ga and Zn.

6. The semiconductor device of claim 1, wherein the first transparent electrode contains an impurity at a higher concentration than the oxide semiconductor layer, and

a portion of the interlayer insulating layer located over the first transparent electrode contains the impurity at a higher concentration than the other portion thereof.

15. The semiconductor device of claim 1, wherein the oxide semiconductor layer includes an In—

Ga—

Zn—

O based semiconductor.

7. A method for fabricating a semiconductor device, the method comprising the steps of:

(a) providing a substrate;

(b) forming a gate electrode and a gate insulating layer on the substrate;

(c) forming an oxide semiconductor film on the gate insulating layer;

(d) forming source and drain electrodes on the oxide semiconductor film;

(e) forming a protective layer to protect a channel region of the oxide semiconductor film, and then performing a resistance lowering process to lower a resistance of a portion of the oxide semiconductor film, thereby forming a first transparent electrode and turning the rest of the oxide semiconductor film where the first transparent electrode is not formed into an oxide semiconductor layer;

(f) forming a dielectric layer over the source and drain electrodes; and

(g) forming a second transparent electrode on the dielectric layer,

wherein at least a portion of the second transparent electrode overlaps with the first transparent electrode with the dielectric layer interposed between them.

8. The method of claim 7, wherein the step (e) is performed between the steps (d) and (f).

9. The method of claim 7, wherein the step (e) is performed between the steps (f) and (g).

10. The method of claim 9, wherein the step (e) includes forming the first transparent electrode by implanting an impurity into a portion of the oxide semiconductor film through the dielectric layer.

11. The method of claim 7, wherein the step (e) is performed after the step (g).

12. The method of claim 11, wherein the step (e) includes forming the first transparent electrode by implanting an impurity into a portion of the oxide semiconductor film through the dielectric layer and the second transparent electrode.

13. The method of claim 8, wherein the protective layer is an oxide insulating layer.

14. The method of claim 7, wherein when viewed along a normal to the substrate, an end portion of the protective layer overlaps with the drain electrode.

16. The method of claim 7, wherein the oxide semiconductor film includes an In—

Ga—

Zn—

O based semiconductor.