SEMICONDUCTOR MEMORY DEVICE

• US 20140367758A1
• Filed: 12/30/2013
• Published: 12/18/2014
• Est. Priority Date: 06/12/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: IZUMIDA, Takashi, NAKAI, TSUKASA, KONDO, MASAKI
• Granted Patent: US 9,018,682 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate;

a channel body provided inside a hole piercing the stacked body, the channel body extending in a stacking direction of the stacked body; and

a memory portion provided between the channel body and each of the plurality of electrode layers;

the hole having a large diameter portion and a small diameter portion, the diameter of the hole being smaller at the small diameter portion than at the large diameter portion,

a thickness of the electrode layer adjacent to the small diameter portion being thicker than a thickness of the electrode layer adjacent to the large diameter portion.

2. The device according to claim 1, wherein

a diameter of the hole is smaller at a lower portion of the hole than at an upper portion of the hole, and

the electrode layer on a lower layer side is thicker than the electrode layer on an upper layer side.

3. The device according to claim 2, wherein a gate length of the electrode layer on the lower layer side is longer than a gate length of the electrode layer on the upper layer side.

4. The device according to claim 2, wherein thicknesses of the electrode layers change in stages.

5. The device according to claim 1, wherein

a diameter of the hole is smaller at an upper portion of the hole than at a lower portion of the hole, and

the electrode layer on an upper layer side is thicker than the electrode layer on a lower layer side.

6. The device according to claim 5, wherein a gate length of the electrode layer on the upper layer side is longer than a gate length of the electrode layer on the lower layer side.

7. The device according to claim 5, wherein thicknesses of the electrode layers change in stages.

8. The device according to claim 1, wherein a side wall of the hole has curvature in a cross section along the stacking direction of the stacked body.

9. The device according to claim 1, wherein a diameter of the hole is smaller at an upper portion of the hole and at a lower portion of the hole than at a central portion of the hole between the upper portion and the lower portion.

10. The device according to claim 9, wherein an interface between the electrode layer and the memory portion has curvature in a cross section along the stacking direction of the stacked body, and the channel body has curvature in the cross section along the stacking direction of the stacked body.

11. The device according to claim 1, wherein a diameter of the hole is larger at an upper portion of the hole and at a lower portion of the hole than at a central portion of the hole between the upper portion and the lower portion.

12. The device according to claim 11, wherein the channel body has curvature in a cross section along the stacking direction of the stacked body, and the memory portion has curvature in the cross section along the stacking direction of the stacked body.

13. The device according to claim 1, wherein the channel body includes:

a pair of columnar portions piercing the stacked body; and

a linking portion linking lower ends of the pair of columnar portions.

14. The device according to claim 13, wherein a lower portion of the columnar portion is finer than an upper portion of the columnar portion.

15. The device according to claim 13, wherein a lower portion of the columnar portion is thicker than an upper portion of the columnar portion.

16. The device according to claim 13, wherein an upper portion of the columnar portion and a lower portion of the columnar portion are finer than a central portion of the columnar portion between the upper portion and the lower portion.

17. The device according to claim 13, wherein an upper portion of the columnar portion and a lower portion of the columnar portion are thicker than a central portion of the columnar portion between the upper portion and the lower portion.

18. The device according to claim 13, wherein a side wall of the columnar portion has curvature in a cross section along the stacking direction of the stacked body.

19. The device according to claim 1, wherein

the memory portion and the channel body are provided in tubular configurations, and

the electrode layers are provided around the channel body with the memory portion interposed.

20. The device according to claim 1, further comprising an upper selection gate provided on the stacked body.