STACKED PACKAGE AND METHOD OF FABRICATING THE SAME

• US 20140367850A1
• Filed: 11/12/2013
• Published: 12/18/2014
• Est. Priority Date: 06/18/2013
• Status: Abandoned Application

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Wang, Lung-Yuan
• Application Number:
  US14/077,771
• Publication Number:
  US 20140367850A1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/25171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

A stacked package and a method of fabricating the same are provided. The stacked package includes: a first package, having a first encapsulant, a first electrical connection structure formed on one surface of the first encapsulant, a plurality of first conductive pillars formed in the first encapsulant, and a first semiconductor chip disposed in the first encapsulant are electrically connected to the first electrical connection structure; and a second package stacked on the first package, wherein the second package has a second encapsulant, a second electrical connection structure formed on the second encapsulant, a second semiconductor, a chip disposed in the second encapsulant and electrically connected to the second electrical connection structure, and a plurality of second conductive pillars formed in the second encapsulant and electrically connected to the first electrical conduction pillars. The stacked package can provide a great number of inputs/outputs for electronic applications.

Claims

1. A method of fabricating a stacked package, comprising:

providing a first package, wherein the first package comprises;

a first encapsulant having a first surface and a second surface opposite to the first surface;

a first electrical connection structure formed on the first surface;

a plurality of first conductive pillars formed in the first encapsulant, each of the first conductive pillars having two ends connected to the first electrical connection structure and exposed from the second surface of the first encapsulant respectively; and

a first semiconductor chip disposed in the first encapsulant and electrically connected to the first electrical connection structure; and

stacking a second package on the first package, wherein the second package comprises;

a second encapsulant having a third surface and a fourth surface opposite to the third surface;

a second electrical connection structure formed on the third surface or the fourth surface of the second encapsulant;

a second semiconductor chip disposed in the second encapsulant and electrically connected to the second electrical connection structure; and

a plurality of second conductive pillars formed in the second encapsulant and electrically connected to the second electrical connection structure;

wherein the first electrical conduction pillars are electrically connected to the second conductive pillars.

2. The method of claim 1, wherein the first electrical connection structure includes a first circuit layer and a first built-up layer formed on the first circuit layer.

3. The method of claim 2, wherein the first package further includes a third electrical connection structure formed on the second surface.

4. The method of claim 3, wherein the third electrical connection structure includes a third circuit layer.

5. The method of claim 3, wherein the first package is formed by:

providing a carrier plate having a metal layer;

forming the first built-up layer on the metal layer;

forming the first circuit layer on the first built-up layer;

forming the first conductive pillars on the first circuit layer;

attaching the first semiconductor chip to the first circuit layer;

forming on the first built-up layer the first encapsulant to encapsulate the first semiconductor chip and the first conductive pillars, with one end of each of the first conductive pillars exposed from a surface of the first encapsulant;

forming on the first encapsulant the third electrical connection structure electrically connected to the first conductive pillars; and

removing the carrier plate and the metal layer.

6. The method of claim 5, wherein the first conductive pillars are formed by:

forming a first dry film on the first built-up layer and the first circuit layer;

forming in the first dry film a plurality of first openings to expose a portion of the first circuit layer to the outside;

forming a first metal part in each of the first openings;

forming a second dry film on the first dry film;

forming in the second dry film a plurality of second openings for exposing the first metal part;

forming in each of the second openings a second metal part connected to the first metal part, such that the first metal part and the second metal part constitute are formed into the first conductive pillar; and

removing the second dry film and the first dry film.

7. The method of claim 3, wherein the first package is formed by:

providing the first built-up layer on which the first circuit layer is formed;

attaching the first built-up layer to a metal layer on a carrier plate via a side of the first built-up layer free from being formed with the first circuit layer;

forming the first conductive pillars on the first circuit layer;

attaching the first semiconductor chip to the first circuit layer;

forming on the first built-up layer the first encapsulant for encapsulating the first semiconductor chip and the first conductive pillars with one end of each of the first conductive pillars exposed from the first encapsulant;

forming on the first encapsulant the third electrical connection structure electrically connected to the first conductive pillars; and

removing the carrier plate and the metal layer.

8. The method of claim 7, wherein the first conductive pillars are formed by:

forming a first dry film on the first built-up layer and the first circuit layer;

forming in the first dry film a plurality of first openings for exposing a portion of the first circuit layer;

forming a first metal part in each of the first openings;

forming a second dry film on the first dry film;

forming in the second dry film a plurality of second openings for exposing the first metal part;

forming in each of the second openings a second metal part connected to the first metal part, wherein the first metal part and the second metal part are formed into the first conductive pillar; and

removing the second dry film and the first dry film.

9. The method of claim 1, wherein the second electrical connection structure includes a second circuit layer.

10. The method of claim 1, further comprising stacking a third package on the second package.

11. The method of claim 1, wherein the first conductive pillars are electrically connected to the second conductive pillars by a solder paste formed between the first package and the second package.

12. The method of claim 1, wherein the second electrical connection structure is formed on the third surface of the second encapsulant, the second package further comprises a second built-up layer formed on the fourth surface of the second encapsulant, and the second package is connected to the first package by the second built-up layer.

13. A stacked package, comprising:

a first package, comprising;

a first encapsulant having a first surface and a second surface opposite to the first surface;

a first electrical connection structure formed on the first surface;

a plurality of first conductive pillars formed in the first encapsulant, and each of the first conductive pillars having two ends connected to the first electrical connection structure and exposed from the second surface respectively; and

a first semiconductor chip disposed in the first encapsulant and electrically connected to the first electrical connection structure; and

a second package stacked on the first package, the second package comprising;

a second encapsulant having a third surface and a fourth surface opposite to the third surface;

a second electrical connection structure formed on the third surface or the fourth surface of the second encapsulant;

a second semiconductor chip disposed in the second encapsulant and electrically connected to the second electrical connection structure; and

a plurality of second conductive pillars formed in the second encapsulant and electrically connected to the second electrical connection structure;

wherein the first electrical conduction pillars are electrically connected to the second conductive pillars.

14. The stacked package of claim 13, wherein the first electrical connection structure includes a first circuit layer and a first built-up layer formed on the first circuit layer.

15. The stacked package of claim 13, wherein the second electrical connection structure includes a second circuit layer.

16. The stacked package of claim 15, wherein the second circuit layer is formed on the third surface of the second encapsulant, the second package further includes a second built-up layer formed on the fourth surface of the second encapsulant, and the second package is electrically connected to the first package by the second built-up layer.

17. The stacked package of claim 13, further comprising a third package stacked on the second package.

18. The stacked package of claim 13, wherein the first package further includes a third electrical connection structure formed on the second surface.

19. The stacked package of claim 13, further comprising a solder paste formed between the first and the second packages, for electrically connecting the first conductive pillars to the second conductive pillars.

20. The stacked package of claim 13, wherein the first conductive pillars are formed by the first metal part and the second metal part.