DELAY CONTROL CIRCUIT

• US 20140368249A1
• Filed: 09/13/2013
• Published: 12/18/2014
• Est. Priority Date: 06/17/2013
• Status: Abandoned Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Kwang Su
• Application Number:
  US14/026,698
• Publication Number:
  US 20140368249A1
• Time in Patent Office: Days
• US Class Current: 327/262
• CPC Class Codes: H03K 2005/00247 using counters
• CPC Class Codes: H03K 2005/0028 using varicaps, e.g. gate capacity of a FET with specially defined threshold, as delaying capacitors
• CPC Class Codes: H03K 5/131 Digitally controlled

Abstract

The present invention relates to a delay control circuit and technology in which the amount of delay can be regularly maintained although Process, Voltage, and Temperature (PVT) conditions are changed. The delay control circuit of the present invention includes a ZQ calibration unit configured to generate an impedance code into which a change of PVT conditions has been incorporated, a voltage trimming unit configured to control a level of a trimming voltage at a calibration node, and a delay compensation unit configured to compensate for the amount of delay by controlling an effective capacitance value of a capacitor.

Claims

1. A delay control circuit, comprising:

a ZQ calibration unit configured to generate an impedance code into which a change of Process, Voltage, and Temperature (PVT) conditions has been incorporated;

a voltage trimming unit configured to control a level of a trimming voltage at a calibration node in response to the impedance code; and

a delay compensation unit configured to compensate for an amount of delay by controlling an effective capacitance value of a capacitor in response to the trimming voltage,

wherein the ZQ calibration unit comprises a reference voltage generator configured to generate a first reference voltage and a second reference voltage in response to the impedance code, and

wherein the ZQ calibration unit controls the impedance code by previously change levels of the first reference voltage and the second reference voltage in response to specifications of a device.

2. The delay control circuit of claim 1, wherein the ZQ calibration unit comprises:

a first comparator configured to compare voltage at the calibration node with the first reference voltage and generate a first comparison signal based on a result of the comparison;

a second comparator configured to compare the voltage at the calibration node with the second reference voltage and generate a second comparison signal based on a result of the comparison;

a hold signal generator configured to activate a hold signal when the first comparison is equal to the second comparison and output the hold signal; and

a counter configured to count the first comparison signal and generate the impedance code based on a result of the counting.

3. The delay control circuit of claim 1, wherein the reference voltage generator comprises:

a plurality of first resistors configured to generate a plurality of division voltages; and

a selector configured to select one voltage of the plurality of division voltages as the first reference voltage and another voltage of the plurality of division voltages as the second reference voltage in response to the impedance code.

4. The delay control circuit of claim 1, wherein the voltage trimming unit comprises:

a code input unit selectively switched in response to the impedance code; and

a voltage division unit configured to control the level of the trimming voltage in response to a switching state of the code input unit.

5. The delay control circuit of claim 1, wherein the delay compensation unit comprises:

a clock driving unit configured to generate an output clock by driving an input clock; and

a compensation unit configured to compensate for an amount of delay of the output clock in response to the trimming voltage.

6. The delay control circuit of claim 5, wherein the clock driving unit comprises an inverter for generating the output clock by inversely driving the input clock.

7. The delay control circuit of claim 5, wherein the delay compensation unit further comprises an input unit for filtering the trimming voltage and outputting the filtered trimming voltage.

8. The delay control circuit of claim 7, wherein the input unit comprises a capacitor coupled between a terminal to which the trimming voltage is inputted and a terminal for a ground voltage.

9. The delay control circuit of claim 5, wherein the compensation unit compensates for RC delay of the input clock by controlling an amount of charging of the output clock in response to the trimming voltage.

10. The delay control circuit of claim 5, wherein the compensation unit comprises:

a switching element switched in response to the trimming voltage and configured to selectively output a source voltage; and

a capacitor configured to have an effective capacitance value controlled in response to the output of the switching element.

11. The delay control circuit of claim 10, wherein the switching element comprises a PMOS transistor coupled between the terminal for the source voltage and the capacitor and configured to have the trimming voltage supplied through a gate terminal of the PMOS transistor.

12. The delay control circuit of claim 11, wherein turn-on resistance of the PMOS transistor is controlled in response to a gate-source voltage of the PMOS transistor varying in response to the trimming voltage.

13. The delay control circuit of claim 10, wherein the capacitor comprises a MOS capacitor coupled between the switching element and a terminal from which the output clock is outputted.

14. The delay control circuit of claim 13, wherein the MOS capacitor comprises a PMOS capacitor.

15. A delay control circuit, comprising:

a ZQ calibration unit configured to generate an impedance code to maintain an impedance value at a target value;

a voltage trimming unit configured to output a trimming voltage to a delay compensation unit; and

the delay compensation unit configured to configured to output an output clock by compensating a delay of an input clock,

wherein the ZQ calibration unit comprises a reference voltage generator configured to generate a first reference voltage and a second reference voltage in which a difference between levels of the first reference voltage and the second reference voltage are controlled in response to the impedance code, and

wherein the ZQ calibration unit controls the impedance code by previously change levels of a reference voltage in response to specifications of a device.

17. The delay circuit of claim 15, further comprising:

a first comparator configured to generate a first comparison signal in response to the first reference voltage and a calibration node voltage; and

a second comparator configured to generate a second comparison signal in response to the second reference voltage and the calibration node voltage.

18. The delay circuit of claim 17, further comprising:

a hold signal generator configured to activate a hold signal in response to a comparison between the first comparison signal and the second comparison signal; and

a counter configured to generate the impedance code to allow the calibration node voltage to have a level between the first reference voltage and the second reference voltage.

19. The delay circuit of claim 15, wherein the delay compensation unit comprises:

a clock driving unit configured to generate the output clock using a compensation inverter; and

a compensation unit configured to compensate for a delay of the input clock by controlling an amount of charging for the output clock.

20. The delay circuit of claim 19, wherein the compensation unit comprises:

a switching element supplied with the trimming voltage and configured to output a source voltage; and

a capacitor configured between the switching element and the output clock to have an effective capacitance value controlled.

16. (canceled)