SHIELDED VERTICALLY STACKED DATA LINE ARCHITECTURE FOR MEMORY

• US 20140369116A1
• Filed: 06/17/2013
• Published: 12/18/2014
• Est. Priority Date: 06/17/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji
• Granted Patent: US 9,147,493 B2
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.

Claims

1. An apparatus comprising:

a first string of vertically stacked memory cells;

a first plurality of vertically stacked data lines, wherein a data line of the first plurality of data lines is coupled to the first string of memory cells through a first select device;

a second string of vertically stacked memory cells; and

a second plurality of vertically stacked data lines, wherein a data line of the second plurality of data lines is coupled to the second string of memory cells through a second select device and is adjacent to the data line coupled to the first string of memory cells,

wherein the apparatus is configured to couple the data line coupled to the first string of memory cells to a shield potential during at least a portion of a memory operation involving a memory cell of the second string of memory cells.

2. The apparatus of claim 1, wherein the first plurality of data lines are located over the first string of memory cells and wherein the second plurality of data lines are located over the second string of memory cells.

3. The apparatus of claim 1, wherein the data line coupled to the first string of memory cells and the data line coupled to the second string of memory cells are coupled to a common page buffer through first and second data line transfer transistors, respectively.

4. The apparatus of claim 3, wherein the first and second data line transfer transistors are configured to alternately couple the common page buffer to a respective one of the data line coupled to the first string of memory cells and the data line coupled to the second string of memory cells.

5. The apparatus of claim 1, wherein the data line coupled to the first string of memory cells and the data line coupled to the second string of memory cells are coupled to a common node through first and second data line shield transistors, respectively.

6. The apparatus of claim 5, wherein the first and second data line shield transistors are configured to alternately couple the common node to a respective one of the data line coupled to the first string of memory cells and the data line coupled to the second string of memory cells.

7. The apparatus of claim 6, wherein the apparatus is configured to provide the shield potential at the common node.

8. The apparatus of claim 1, wherein the apparatus further comprises a controller, wherein the controller is configured to cause the data line coupled to the first string of memory cells to be coupled to the shield potential during at least a portion of the memory operation involving the memory cell of the second string of memory cells.

9. The apparatus of claim 1, wherein the memory operation comprises sensing the memory cell of the second string.

10. The apparatus of claim 1, wherein the memory operation comprises programming the memory cell of the second string.

11. The apparatus of claim 1, wherein the second string of memory cells is adjacent to the first string of memory cells in a direction orthogonal to a direction in which the first plurality of data lines extend, the apparatus further comprising:

a third string of vertically stacked memory cells adjacent to the first string of memory cells in the direction in which the first plurality of data lines extend, wherein a second data line of the first plurality of data lines is coupled to the third string of memory cells through a third select device; and

a fourth string of vertically stacked memory cells adjacent to the second string of memory cells in a direction in which the second plurality of data lines extend, wherein a second data line of the second plurality of data lines is coupled to the fourth string of memory cells through a fourth select device and is adjacent to the second data line of the first plurality of data lines.

12. The apparatus of claim 11, wherein the apparatus is configured to couple the second data line coupled to the third string of memory cells to the shield potential during at least a portion of a memory operation involving a memory cell of the fourth string of memory cells.

13. The apparatus of claim 11, wherein the apparatus is configured to couple the second data line coupled to the fourth string of memory cells to the shield potential during at least a portion of a memory operation involving a memory cell of the third string of memory cells.

14. The apparatus of claim 13, further comprising:

a fifth string of vertically stacked memory cells adjacent to the third string of memory cells in the direction in which the first plurality of data lines extend, wherein a third data line of the first plurality of data lines is coupled to the fifth string of memory cells through a fifth select device; and

a sixth string of vertically stacked memory cells adjacent to the fourth string of memory cells in the direction in which the second plurality of data lines extend, wherein a third data line of the second plurality of data lines is coupled to the sixth string of memory cells through a sixth select device and is adjacent to the third data line of the first plurality of data lines.

15. The apparatus of claim 14, wherein the apparatus is configured to couple the third data line coupled to the fifth string of memory cells to the shield potential during at least a portion of a memory operation involving a memory cell of the sixth string of memory cells.

16. The apparatus of claim 1, wherein the first and second select devices comprise first and second transistors.

17. The apparatus of claim 16, wherein control gates of the first and second transistors are commonly coupled.

18. The apparatus of claim 16, wherein the first and second transistors comprise first and second select gate drain transistors.

19. The apparatus of claim 18, wherein the first string of memory cells are associated with a first pillar of semiconductor material, and wherein the second string of memory cells are associated with a second pillar of semiconductor material.

20. The apparatus of claim 19, wherein a memory cell of the first string of memory cells at least partially surrounds the first pillar of semiconductor material, and wherein the memory cell of the second string of memory cells at least partially surrounds the second pillar of semiconductor material.

21. The apparatus of claim 1, wherein a first memory cell of the first string of memory cells and a first memory cell of the second string of memory cells are commonly coupled to a first control gate formed in a first tier above a substrate, and wherein a second memory cell of the first string of memory cells and a second memory cell of the second string of memory cells are commonly coupled to a second control gate formed in a second tier above the substrate.

22. The apparatus of claim 1, wherein the first and second strings are coupled to a common source through first and second select gate source transistors, wherein control gates of the first and second select gate source transistors are commonly coupled.

23. The apparatus of claim 1, wherein the second plurality of vertically stacked data lines are adjacent to the first plurality of vertically stacked data lines.

24. The apparatus of claim 1, wherein the first string of memory cells is adjacent to the second string of memory cells.

25. The apparatus of claim 1, wherein the data line coupled to the first string of memory cells and the data line coupled to the second string of memory cells are formed in a same tier above the first and second strings of memory cells.

26. The apparatus of claim 25, wherein the data line coupled to the first string of memory cells and the data line coupled to the second string of memory cells are formed from a same layer of conductive material formed in the same tier above the first and second strings of memory cells.

27. The apparatus of claim 1, wherein the memory operation comprises sensing the memory cell of the second string of memory cells and the shield potential comprises a ground potential.

28. The apparatus of claim 1, wherein the memory operation comprises programming the memory cell of the second string of memory cells and the shield potential comprises an inhibit potential.

29. The apparatus of claim 1, wherein the apparatus comprises a memory device including the first and second strings of memory cells.

30. The apparatus of claim 29, wherein the apparatus comprises a system including the memory device.

31. The apparatus of claim 1, wherein the first plurality of vertically stacked data lines comprise vertically aligned data lines.

32. The apparatus of claim 1, wherein at least one of the first plurality of vertically stacked data lines is offset from another data line of the first plurality of data lines.

33. An apparatus comprising:

a first string of vertically stacked memory cells;

a second string of vertically stacked memory cells adjacent to the first string of memory cells;

a third string of vertically stacked memory cells adjacent to the second string of memory cells; and

a plurality of vertically stacked data lines above the first, second and third string of memory cells, wherein a first data line of the plurality of data lines is coupled to the first string of memory cells through a first select device, a second data line of the plurality of data lines is coupled to the second string of memory cells through a second select device, a third data line of the plurality of data lines is coupled to the third string of memory cells through a third select device, the second data line being above the first data line, and the third data line being above the second data line,

wherein the apparatus is configured to couple the first and third data lines to a shield potential during at least a portion of a memory operation involving a memory cell of the second string of memory cells.

34. The apparatus of claim 33, further comprising:

a fourth string of vertically stacked memory cells adjacent to the third string of memory cells; and

a fourth data line of the plurality of data lines coupled to the fourth string of memory cells through a fourth select device, wherein the fourth data line is above the third data line.

35. The apparatus of claim 33, wherein the plurality of vertically stacked data lines are over the first, second and third strings.

36. The apparatus of claim 33, wherein the second string of memory cells is adjacent to the first string of memory cells in a direction in which the first data line extends.

37. The apparatus of claim 36, wherein the third string of memory cells is adjacent to the second string of memory cells in a direction in which the second data line extends.

38. The apparatus of claim 37, wherein the first and second data lines extend in the same direction.

39. The apparatus of claim 33, wherein the plurality of data lines comprises a first plurality of data lines, the apparatus further comprising:

a fourth string of vertically stacked memory cells; and

a second plurality of vertically stacked data lines, wherein a data line of the second plurality of data lines is coupled to the fourth string of memory cells through a fourth select device and is adjacent to the first data line of the first plurality of data lines,

wherein the apparatus is configured to couple the first data line to the shield potential during at least a portion of a memory operation involving a memory cell of the fourth string of memory cells.

40. The apparatus of claim 39, wherein the second plurality of data lines are above the fourth string of memory cells and adjacent to the first plurality of data lines, and wherein the fourth string of memory cells is adjacent to the first string of memory cells in a direction orthogonal to a direction in which the first data line extends.

41. An apparatus comprising:

a plurality of vertically stacked data lines, each vertically stacked data line of the plurality of vertically stacked data lines coupled to a respective one of strings of memory cells; and

a node switchably coupled to the plurality of vertically stacked data lines and configured to provide a plurality of potentials responsive to different memory operations wherein alternate ones of the plurality of vertically stacked data lines are configured to be switched to the node during a particular memory operation.