SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20140370654A1
• Filed: 09/02/2014
• Published: 12/18/2014
• Est. Priority Date: 11/25/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Granted Patent: US 9,991,293 B2
• Time in Patent Office: Days
• US Class Current: 438/104
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/13625 Patterning using multi-mask exposure
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/1315 comprising structures specially adapted for lowering the resistance

Abstract

A step for forming an island-shaped semiconductor layer of a semiconductor device used in a display device is omitted in order to manufacture the semiconductor device with high productivity and low cost. The semiconductor device is manufactured through four photolithography processes: four steps for forming a gate electrode, for forming a source electrode and a drain electrode, for forming a contact hole, and for forming a pixel electrode. In the step for forming the contact hole, a groove portion in which a semiconductor layer is removed is formed, whereby formation of a parasitic transistor is prevented. An oxide semiconductor is used as a material of the semiconductor layer in which a channel is formed, and an oxide semiconductor having a higher insulating property than the semiconductor layer is provided over the semiconductor layer.

Claims

1. (canceled)

2. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate by a first photolithography process;

forming a gate insulating layer over the gate electrode;

forming a semiconductor layer including a first oxide semiconductor over the gate insulating layer;

forming a source electrode and a drain electrode over the semiconductor layer by a second photolithography process;

forming a layer including a second oxide semiconductor having a higher insulating property than the semiconductor layer over the source electrode and the drain electrode;

forming a contact hole by selectively removing a portion of the layer that overlaps with the drain electrode and forming a groove portion by removing a portion of the layer, the semiconductor layer, and the gate insulating layer, by a third photolithography process; and

forming a pixel electrode over the layer by a fourth photolithography process.

3. The method for manufacturing the semiconductor device according to claim 2,

wherein the layer includes an oxide material including In, an element M, and Zn, and

wherein the element M is a group 3A element, a group 4A element, or a group 4B element.

4. The method for manufacturing the semiconductor device according to claim 3, wherein the layer is formed of In-M-Zn-based oxide including the element M.

5. The method for manufacturing the semiconductor device according to claim 4, wherein the element M is Ti, Zr, Hf, Ge, Ce, or Y.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming a semiconductor layer including a first oxide semiconductor over the gate insulating layer;

forming a source electrode and a drain electrode over the semiconductor layer;

forming a layer including a second oxide semiconductor having a higher insulating property than the semiconductor layer over the source electrode and the drain electrode;

forming a contact hole by selectively removing a portion of the layer that overlaps with the drain electrode; and

forming a pixel electrode over the layer.

7. The method for manufacturing the semiconductor device according to claim 6, further comprising forming a groove portion by removing a portion of the layer, the semiconductor layer, and the gate insulating layer.

8. The method for manufacturing the semiconductor device according to claim 6,

wherein the layer includes an oxide material including In, an element M, and Zn, and

wherein the element M is a group 3A element, a group 4A element, or a group 4B element.

9. The method for manufacturing the semiconductor device according to claim 8, wherein the layer is formed of In-M-Zn-based oxide including the element M.

10. The method for manufacturing the semiconductor device according to claim 9, wherein the element M is Ti, Zr, Hf, Ge, Ce, or Y.