METHOD OF FORMING POLYSILICON IN A TRENCH

• US 20140370700A1
• Filed: 06/12/2014
• Published: 12/18/2014
• Est. Priority Date: 06/14/2013
• Status: Active Grant

• Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Tong, Liang
• Granted Patent: US 9,147,739 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode

Abstract

Disclosed herein are methods for forming polysilicon in a trench. The sacrificial layer having a high etching rate is applied on the surface of polysilicon after polysilicon is formed on the surface of the substrate and in the trench. The sacrificial layer can provide a flat surface. With the sacrificial layer as a sacrificial mask layer, polysilicon can be etched as having a flat surface. The present disclosure avoids using the CMP process, simplifies the manufacturing process, and reduces the production cost. Moreover, the oxide layer formed thereafter can meet the requirement of current applications.

Claims

1. A method for forming polysilicon in a trench, comprising:

providing a substrate;

forming a first dielectric layer on said substrate;

forming an opening in said first dielectric layer by etching;

forming a trench in said substrate by etching through said opening;

forming a second dielectric layer on sidewalls of said trench;

forming polysilicon on a surface of said substrate and on a surface of said second dielectric layer in said trench;

applying a sacrificial layer on a surface of polysilicon; and

removing said sacrificial layer and the portion of polysilicon on said surface of said substrate successively by etching, while the portion of polysilicon remaining in said trench is etched to a predetermined depth below said surface of said substrate.

2. The method according to claim 1, wherein said sacrificial layer is made of photoresist or spin-on glass.

3. The method according to claim 2, wherein said sacrificial layer has a thickness in the range between 200 angstroms and 2 micrometers.

4. The method according to claim 1, wherein said first dielectric layer is made of silicon oxide.

5. The method according to claim 4, wherein said first dielectric layer has a thickness in the range between 10 angstroms and 5000 angstroms.

6. The method according to claim 1, wherein after forming said first dielectric layer and before forming said opening, further comprises forming a mask layer on said first dielectric layer.

7. The method according to claim 6, wherein said mask layer is a patterned photoresist layer.

8. The method according to claim 6, wherein said mask layer has a thickness in the range between 100 angstroms and 8000 angstroms.

9. The method according to claim 1, wherein said second dielectric layer is made of silicon oxide.

10. The method according to claim 9, wherein said second dielectric layer has a thickness in the range between 100 angstroms and 8000 angstroms.