FAILURE DETECTION IN HIGH-PERFORMANCE CLUSTERS AND COMPUTERS USING CHAOTIC MAP COMPUTATIONS

• US 20140372802A1
• Filed: 06/17/2013
• Published: 12/18/2014
• Est. Priority Date: 06/17/2013
• Status: Active Grant

• Current Assignee: UT-Battelle LLC
• Original Assignee: UT-Battelle LLC
• Inventors: Rao, Nageswara S.
• Granted Patent: US 9,122,603 B2
• Time in Patent Office: Days
• US Class Current: 714/37
• CPC Class Codes: G06F 11/0709 in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/3006 where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems multiprogramming arrangements G06F9/46; allocation of resources G06F9/50
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling

Abstract

A programmable media includes a processing unit capable of independent operation in a machine that is capable of executing 10¹⁸ floating point operations per second. The processing unit is in communication with a memory element and an interconnect that couples computing nodes. The programmable media includes a logical unit configured to execute arithmetic functions, comparative functions, and/or logical functions. The processing unit is configured to detect computing component failures, memory element failures and/or interconnect failures by executing programming threads that generate one or more chaotic map trajectories. The central processing unit or graphical processing unit is configured to detect a computing component failure, memory element failure and/or an interconnect failure through an automated comparison of signal trajectories generated by the chaotic maps.

Claims

1. A failure detection system comprising:

an exascale machine comprising a supercomputer or a cluster capable of executing at least one exaFLOPS;

a plurality of processors that comprise part of the exasacle machine programmed to execute a programming thread that generates one or more chaotic map trajectories;

where at least one of the plurality of processors is further programmed to detect a component failure through an automated comparison of signal trajectories generated by a plurality of chaotic maps.

2. The failure detection system of claim 1 where at least one of the plurality of processors is programmed to detect component failures through the execution of inverse-pair operations.

3. The failure detection system of claim 1 where at least one of the plurality of processors is programmed to transmit a state variable across an interconnect.

4. The failure detection system of claim 1 where the plurality of processors render a plurality of pipeline chains.

5. The failure detection system of claim 1 where the trajectories are generated by a chaotic Poincare map.

6. The failure detection system of claim 1 where trajectories are generated by identity maps.

7. The failure detection system of claim 1 where the trajectories are generated by a chaotic Poincare map and an identity map.

8. The failure detection system of claim 1 where the at least one of the processors detects a component failure by a comparison of a plurality of chaotic Poincare maps.

9. The failure detection system of claim 1 where the at least one of the processors detects a component failure through a difference calculation of chaotic map trajectories.

10. The failure detection system of claim 1 where the chaotic map comprises a Poincare logistic map.

11. The failure detection system of claim 1 where the chaotic map comprises a Poincare tent map.

12. The failure detection system of claim 1 where the chaotic map comprises a Poincare Henon map.

13. The failure detection system of claim 1 where the plurality of processors comprise a plurality of single or multi-core central processor units.

14. The failure detection system of claim 1 where the plurality of processors comprise a plurality of graphical processor units.

15. The failure detection system of claim 1 where the processing threads are inserted into application code that traces the execution paths of at least one tracer code.

16. A programmable media comprising:

a single or multi-core central processing unit or a graphical processing unit, capable of independent operation in an exascale machine in communication with a memory element and an interconnect that couples computing elements;

at least one logical unit configured to execute arithmetic, comparative functions, and logical functions;

the central processing unit or graphical processing unit configured to detect one or more computing node or interconnect failures through programming threads that generate one or more chaotic map trajectories and being configured to detect a computing node failure or an interconnect failure through an automated comparison of signal trajectories generated by the one or more chaotic maps.

17. The programmable media of claim 16 where the central processing unit or graphical processing unit is programmed to detect the computing node failure and the interconnect failure through the execution of inverse-pair operations.

18. The programmable media of claim 16 where the central processing unit or graphical processing unit is programmed to transmit a state variable across an interconnect.

19. The programmable media of claim 16 where the central processing unit or graphical processing unit is programmed to render a plurality of pipeline chains.

20. The programmable media of claim 16 where the trajectories comprise a chaotic Poincare map.

21. The programmable media of claim 16 where the central processing unit or graphical processing unit is configured to execute tracer threads inserted into application code that generates the execution paths of at least one tracer code.