MEMORY CONTROLLER OPERATING METHOD FOR READ OPERATIONS IN SYSTEM HAVING NONVOLATILE MEMORY DEVICE

• US 20140372831A1
• Filed: 06/13/2014
• Published: 12/18/2014
• Est. Priority Date: 06/14/2013
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: OH, SANGYOON, KIM, DONG-MIN, KIM, YOUNGMOON
• Application Number:
  US14/303,646
• Publication Number:
  US 20140372831A1
• Time in Patent Office: Days
• US Class Current: 714/764
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence

Abstract

A memory controller operating method includes executing a read operation directed to read data including a correctable data unit and an uncorrectable data unit, the uncorrectable data unit containing data that is uncorrectable using a normal error correction operation. The method further including; performing the normal error correction operation on the correctable data unit to generate partial read data, communicating dummy data instead of the uncorrectable data unit along with the partial read data from the memory controller to a host, and performing an enhanced error correction operation on the uncorrectable data unit while at least in part the dummy data and partial data are being communicated from the memory controller to the host.

Claims

1. A memory controller operating method, comprising:

controlling execution of a read operation directed to read data stored in a nonvolatile memory device, the read data including a plurality of data units, each of the plurality of the data units is identified as one of a correctable data unit and an uncorrectable data unit, wherein the uncorrectable data unit contains data that is uncorrectable using a normal error correction operation;

performing the normal error correction operation on at least one correctable data unit of the plurality of data units to generate partial read data;

communicating dummy data instead of at least one uncorrectable data unit of the plurality of data units along with the partial read data from the memory controller to a host; and

performing an enhanced error correction operation on the uncorrectable data unit while at least in part the dummy data and partial data are being communicated from the memory controller to the host.

2. The method of claim 1, further comprising:

communicating a corrected version of the at least one uncorrectable data unit from the memory controller to the host upon completion of the enhanced error correction operation.

3. The method of claim 2, wherein the dummy data is data selected from a group consisting of;

data of the at least one uncorrectable read unit, data having a random pattern, and data having a predetermined pattern.

4. The method of claim 1 further comprising:

receiving a read command from the host in the memory controller that initiates the read operation and identifies the read data as stored in the nonvolatile memory device.

5. The method of claim 4, further comprising:

allocating buffer units in a buffer memory of the memory controller to receive the plurality of data units of the read data; and

storing each one of the plurality of data units in a respective one of the allocated buffer units.

6. The method of claim 5, further comprising:

on a data unit-by-data unit basis for the plurality of data units stored in the allocated buffer units, using an error correction coding (ECC) circuit to identify whether data associated with each one of the plurality of data units is correctable data.

7. The method of claim 6, wherein the identifying of whether data associated with each one of the plurality of data units is correctable data is performed using the normal error correction operation as executed by the ECC circuit.

8. The method of claim 2, further comprising:

allocating buffer units in a buffer memory of the memory controller to receive the plurality of data units of the read data;

storing each one of the plurality of data units in a respective one of the allocated buffer units, wherein at least one of the buffers stores the at least one uncorrectable data unit,

wherein the communicating of the corrected version of the at least one uncorrectable data unit from the memory controller to the host upon completion of the enhanced error correction operation is performed by overwriting the at least one uncorrectable data unit stored in the at least one buffer unit with the corrected version of the at least one uncorrectable data unit.

9. The method of claim 8 further comprising:

updating a buffer unit information based on the allocation of the buffer units in a buffer table.

10. The method of claim 9, wherein the buffer unit information includes offset information and size information associated with each one of the allocated buffer units.

11. The method of claim 10, further comprising:

storing error information associated with the uncorrectable data unit in the buffer table.

12. A system comprising:

a nonvolatile memory device; and

a memory controller configured to control execution of a read operation directed to read data stored in the nonvolatile memory device, wherein the read data includes a plurality of data units, each of the plurality of data units is identified as one of a correctable data unit and an uncorrectable data unit, the data of the uncorrectable data unit being uncorrectable using a normal error correction operation,

the memory controller being further configured to perform the normal error correction operation on the at least one correctable data unit of the plurality of data units to generate partial read data, communicate dummy data instead of the at least one uncorrectable data unit along with the partial read data to the host, and perform an enhanced error correction operation on the at least one uncorrectable data unit while at least in part the dummy data and partial data are being communicated from the memory controller to the host.

13. The system of claim 12, wherein the memory controller is further configured to communicate a corrected version of the at least one uncorrectable data unit to the host upon completion of the enhanced error correction operation.

14. The system of claim 13, wherein the dummy data is data selected from a group consisting of;

data of the at least one uncorrectable read unit, data having a random pattern, and data having a predetermined pattern.

15. The system of claim 12, wherein the memory controller comprises a buffer memory and is further configured to allocate buffer units of the buffer memory to receive the plurality of data units of the read data, and store each one of the plurality of data units in a respective one of the allocated buffer units.

16. The system of claim 15, wherein the memory controller comprises an error correction coding (ECC) circuit and is further configured on a data unit-by-data unit basis for

the plurality of data units stored in the allocated buffer units to identify whether data associated with each one of the plurality of data units is correctable data.

17. The system of claim 16, wherein the identifying of whether data associated with each one of the plurality of data units is correctable data is performed using the normal error correction operation as executed by the ECC circuit.

18. The system of claim 12, wherein the memory controller comprises a buffer memory and is further configured to allocate buffer units, store the at least one correctable data unit, which is corrected an error by the normal error correction operation, in the allocated buffer units.

19. An operating method for a memory controller, comprising:

receiving a first command from host identifying a first read operation directed to first read data stored in a nonvolatile memory device, the first read data including a correctable data unit and an uncorrectable data unit, wherein the uncorrectable data unit contains data that is uncorrectable using a normal error correction operation;

receiving a second command from the host identifying a second read operation directed to second read data stored in the nonvolatile memory device;

performing the normal error correction operation on the correctable data unit of the first read data to generate partial read data;

communicating dummy data instead of the uncorrectable data unit along with the partial read data from the memory controller to a host; and

performing an enhanced error correction operation on the uncorrectable data unit while at least in part executing the second read operation.

20. The operating method of claim 19, further comprising:

allocating buffer units in a buffer memory of the memory controller to receive a plurality of data units of the first read data;

storing each one of the plurality of data units in a respective one of the allocated buffer units; and

on a data unit-by-data unit basis for the plurality of data units stored in the allocated buffer units, using an error correction coding (ECC) circuit to identify whether data associated with each one of the plurality of data units is correctable data using the normal error correction operation as executed by the ECC circuit.