METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND RELATED SEMICONDUCTOR DEVICES AND STRUCTURES

• US 20140374811A1
• Filed: 06/19/2013
• Published: 12/25/2014
• Est. Priority Date: 06/19/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Larsen, Christopher J., Daycock, David A., Shrotri, Kunal
• Granted Patent: US 9,153,455 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control region.

Claims

1. A method of fanning a semiconductor device structure, the method comprising:

forming a liner on a conductive material on a base material;

exposing the liner to a radical oxidation treatment to form a densified liner on the conductive material; and

patterning the base material while protecting the conductive material from patterning with the densified liner.

2. The method of claim 1, wherein forming a liner on a conductive material on a base material comprises forming the liner on a conductive material comprising at least one of a metal, a metal silicide, and a metal nitride.

3. The method of claim 1, wherein forming a liner on a conductive material on a base material comprises forming at least one of an oxide, a nitride, and an oxynitride on the conductive material.

4. The method of claim 1, wherein exposing the liner to a radical oxidation treatment comprises exposing the liner to oxygen radicals, hydrogen radicals, and hydroxyl radicals.

5. The method of claim 4, wherein exposing the liner to oxygen radicals, hydrogen radicals, and hydroxyl radicals comprises exposing the liner to the oxygen radicals, the hydrogen radicals, and the hydroxyl radicals at a temperature of up to about 950°

C.

6. The method of claim 1, wherein exposing the liner to a radical oxidation treatment comprises exposing the liner to a radical oxidation treatment utilizing a gas mixture comprising oxygen and at least about 0.5% hydrogen.

7. The method of claim 1, wherein patterning the base material while protecting the conductive material from patterning with the densified liner comprises etching the base material without etching the conductive material.

8. A method of forming a memory cell, the method comprising:

forming a control gate region over a dielectric material;

substantially conformally forming a liner on at least sidewalls of the control gate region;

exposing the liner to oxygen radicals, hydrogen radicals, and heat to form a densified liner on at least the sidewalls of the control gate region; and

selectively removing portions of the dielectric material using the densified liner to protect the sidewalls of the control gate region from exposure.

9. The method of claim 8, wherein forming a control gate region comprises forming a doped conductive material over the dielectric material.

10. The method of claim 9, wherein forming a control gate region further comprises forming a metallic material over the doped conductive material.

11. The method of claim 8, further comprising forming a capping region over the control gate region.

12. The method of claim 11, wherein conformally forming a liner on at least sidewalls of the control gate region comprises forming the liner on the capping region.

13. The method of claim 8, wherein selectively removing portions of the dielectric material using the densified liner to protect the sidewalls of the control gate region from exposure comprises selectively removing portions of the dielectric material and a conductive material underlying the dielectric material without exposing the sidewalls of the control gate region.

14. A method of forming an array of memory cells, the method comprising:

forming features comprising at least one conductive material on a dielectric material exposed between the features;

forming an oxide liner on sidewalls of the features and on the dielectric material;

exposing the oxide liner to an in situ steam generation (ISSG) process to form a densified oxide liner on the sidewalls of the features; and

removing a portion of the dielectric material and preventing exposure of the at least one conductive material with the densified oxide liner.

15. The method of claim 14, wherein forming an oxide liner on sidewalls of the features and on the dielectric material comprises forming the oxide liner by atomic layer deposition.

16. The method of claim 14, wherein exposing the oxide liner to an in situ steam generation (ISSG) process comprises exposing the oxide liner to a gas mixture consisting of hydrogen radicals and oxygen radicals at a temperature of less than about 900°

C.

17. The method of claim 16, wherein exposing the oxide liner to a gas mixture consisting of hydrogen radicals and oxygen radicals at a temperature of less than about 900°

C. comprises exposing the oxide liner to the gas mixture at the temperature for an exposure time of about twelve seconds.

18. The method of claim 16, wherein exposing the oxide liner to a gas mixture consisting of hydrogen radicals and oxygen radicals comprises forming the hydrogen radicals and the oxygen radicals from a gas mixture consisting of about 18% hydrogen and about 82% oxygen.

19. A semiconductor device structure, comprising:

a plurality of features extending from a substrate, neighboring features of the plurality spaced from one another by a trench exposing a portion of the substrate, at least one feature of the plurality comprising;

a region of at least one conductive material over the substrate; and

a liner on sidewalls of the region of the at least one conductive material.

20. The semiconductor device structure of claim 19, wherein a portion of the liner is disposed on the sidewalls of the region of the at least one conductive material and another portion of the liner is disposed on sidewalls of a capping region over the region of the at least one conductive material, the portion of the liner disposed on the sidewalls of the capping region having a greater thickness than the portion of the liner disposed on the sidewalls of the region of the at least one conductive material.

21. The semiconductor device structure of claim 19, wherein the liner comprises a densified liner.

22. A semiconductor device, comprising:

a plurality of memory cells, at least one memory cell of the plurality comprising;

a control gate region comprising a metallic material;

a capping region overlying the control gate region, sidewalls of the control gate region substantially aligning with sidewalls of the capping region; and

a charge structure under the control gate region.

23. The semiconductor device of claim 22, wherein the metallic material consists of an elemental metal.

24. The semiconductor device of claim 22, wherein the control gate region comprises at least one region of the metallic material and at least one region of a doped conductive material.