ENHANCING SCHOTTKY BREAKDOWN VOLTAGE (BV) WITHOUT AFFECTING AN INTEGRATED MOSFET-SCHOTTKY DEVICE LAYOUT

• US 20140374823A1
• Filed: 06/24/2013
• Published: 12/25/2014
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Wang, Xiaobin, Ho, Moses
• Granted Patent: US 9,093,521 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

Claims

1. A semiconductor power device comprising an active cell area having a plurality of power transistor cells supported on a semiconductor substrate, wherein:

said power transistor cells are integrated and functioning together with a plurality of Schottky diodes disposed in areas between said power transistor cells on said semiconductor substrate wherein each of said active transistor cells comprising a trenched gate surrounded by a body region encompassing a source region of opposite conductivity type therein;

a heavy body region having a body dopant concentration higher than the body region disposed from a top surface of the substrate into the body region adjacent the source region and away from an outer edge of the body region distant from the trenched gate;

wherein a Schottky junction barrier metal overlaying a space between adjacent body regions forming a Schottky diode there between, said adjacent body regions being disposed in a mesa of the semiconductor substrate between two adjacent trenched gate.

2. The semiconductor power device of claim 1 wherein:

said heavy body region extends deeper than the source region.

3. The semiconductor power device of claim 1 further comprising:

a Schottky barrier height adjustment layer on a top portion of the semiconductor substrate in the space between adjacent body regions.

4. The semiconductor power device of claim 1 wherein:

said space between adjacent body regions being narrower than a space between corresponding adjacent heavy body regions each respectively disposed in one of the adjacent body regions.

5. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising MOSFET transistor cells configured to surround an area of planar Schottky diode with said heavy body regions surrounding the Schottky diode forming Junction Barrier Controlled Schottky (JBS).

6. The semiconductor power device of claim 5 wherein:

each of said heavy body regions being surrounded by a portion of lightly doped body region between the outer edge of the body region and an outer edge of the heavy body region thus improving a breakdown of the JBS.

7. The semiconductor power device of claim 1 wherein:

said semiconductor substrate comprises an epitaxial layer on an upper portion having a gradually increasing dopant concentration along a vertical direction having a lighter dopant concentration near a top surface of said epitaxial layer.

8. The semiconductor power device of claim 1 wherein:

said body regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer, said upper source dopant layer extends in said substrate to a depth deeper than said heavy body region.

9. The semiconductor power device of claim 8 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.

10. The semiconductor power device of claim 1 wherein:

said trenched gate penetrates through a central portion of the source and the body regions into the substrate of source dopant conductivity.

11. A semiconductor power device comprising an active cell area having a plurality of power transistor cells supported on a semiconductor substrate, each of said power transistor cells comprising a trenched gate surrounded by a body region encompassing a source region therein having an opposite conductivity type from said body region, wherein:

said power transistor cells are configured to surround a plurality of junction barrier Schottky (JBS) there between each comprising a planar Schottky diode and a heavy body region surrounding the planar Schottky diode;

said heavy body region having a body dopant concentration higher than the body region being surrounded by a portion of lightly doped body region between the outer edge of the body region and an outer edge of the heavy body region thus improving a breakdown of the JBS; and

a Schottky junction barrier metal on top of said semiconductor substrate contacting the source region, the body region, the heavy body region and a Schottky diode region encompassed by the body region.

12. The semiconductor power device of claim 11 wherein:

said heavy body region extends deeper than the source region.

13. The semiconductor power device of claim 11 further comprising:

a Schottky barrier height adjustment layer on a top portion of the semiconductor substrate in the space between adjacent body regions.

14. The semiconductor power device of claim 11 wherein:

said power transistor cells further comprising MOSFET transistor cells configured to surround an area of planar Schottky diode with said heavy body regions surrounding the Schottky diode forming Junction Barrier Controlled Schottky (JBS).

15. The semiconductor power device of claim 11 wherein:

said semiconductor substrate comprises an epitaxial layer on an upper portion having a gradually increasing dopant concentration along a vertical direction having a lighter dopant concentration near a top surface of said epitaxial layer.

16. The semiconductor power device of claim 11 wherein:

said body regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer, said upper source dopant layer extends in said substrate to a depth deeper than said heavy body region.

17. The semiconductor power device of claim 16 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.

18. The semiconductor power device of claim 11 wherein:

said trenched gate penetrates through a bottom of the source region and a bottom of the body region into the substrate of source dopant conductivity and surrounds the source region and the body region.

19. A semiconductor power device supported on a semiconductor substrate comprising an active cell area having a plurality of power transistor cells wherein:

each of said power transistor cells comprising a Schottky junction barrier metal overlaying a mesa surface of the semiconductor substrate between a pair of trenched gate;

a planar Schottky diode disposed in a central surface area of the mesa between a pair of body regions each extending into a mesa region shallower than the trenched gates from a portion of the mesa surface next to one of the pair of trench gate;

each of the body regions encompassing a source region extending from a top surface of the body region next to the corresponding trenched gate into a portion of the body region shallower than a bottom of the body region and a heavy body region having a higher dopant concentration than the body region from a top surface of the body region next to the source region into a portion of the mesa region shallower than the bottom of body region,

wherein a gap between the pair of body regions is narrower than a gap between the pair of heavy body regions.

20. The semiconductor power device of claim 19 wherein:

said heavy body region extends deeper than the source region.

21. The semiconductor power device of claim 19 further comprising:

a Schottky barrier height adjustment layer in a central surface area of the mesa between the pair of body regions.

22. The semiconductor power device of claim 19 wherein:

said power transistor cells further comprising MOSFET transistor cells configured to comprise an area of planar Schottky diode with said heavy body regions surrounding the Schottky diode forming Junction Barrier Controlled Schottky (JBS).

23. The semiconductor power device of claim 22 wherein:

each of said heavy body regions being surrounded by a portion of lightly doped body region between an outer edge of the body region and an outer edge of the heavy body region thus improving a breakdown of the JBS.

24. The semiconductor power device of claim 19 wherein:

said semiconductor substrate comprises an epitaxial layer on an upper portion having a gradually increasing dopant concentration along a vertical direction having a lighter dopant concentration near a top surface of said epitaxial layer.

25. The semiconductor power device of claim 19 wherein:

said body regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer, said upper source dopant layer extends in said substrate to a depth deeper than said heavy body region.

26. The semiconductor power device of claim 25 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.