Power Semiconductor Device with Contiguous Gate Trenches and Offset Source Trenches

• US 20140374825A1
• Filed: 06/09/2014
• Published: 12/25/2014
• Est. Priority Date: 06/21/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kelkar, Kapil, Henson, Timothy D., Ma, Ling, Ranjan, Niraj, Charles, Alain, Burke, Hugo
• Granted Patent: US 9,818,743 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another.

Claims

1. A power semiconductor device comprising:

a plurality of source trenches adjacent to a plurality of source regions;

said plurality of source trenches extending from a top surface of a semiconductor substrate into said semiconductor substrate,

a plurality of gate trenches extending from said top surface into said semiconductor substrate, said plurality of gate trenches forming hexagonal patterns;

a contiguous formation of said plurality of gate trenches separating said plurality of source trenches from one another.

2. The power semiconductor device of claim 1, wherein at least one source contact is electrically coupled to said plurality of source regions.

3. The power semiconductor device of claim 2, wherein each of said plurality of gate trenches is electrically insulated from said at least one source contact by a gate insulator.

4. The power semiconductor device of claim 1, wherein a source trench dielectric lines each of said plurality of source trenches.

5. The power semiconductor device of claim 1, wherein a gate trench dielectric lines each of said plurality of gate trenches.

6. The power semiconductor device of claim 1, wherein said contiguous formation of said plurality of gate trenches completely surrounds each of said plurality of source trenches.

7. The power semiconductor device of claim 1, wherein said plurality of gate trenches are spaced substantially equally between each of said plurality of source trenches.

8. The power semiconductor device of claim 1, wherein a drain region of said semiconductor substrate is electrically coupled to a drain contact.

9. The power semiconductor device of claim 1, wherein said plurality of source trenches are offset from one another.

10. The power semiconductor device of claim 1, wherein said plurality of source trenches are substantially equally spaced from one another.

11. A power semiconductor device comprising:

a plurality of source trenches adjacent to a plurality of source regions;

said plurality of source trenches extending from a top surface of a semiconductor substrate into said semiconductor substrate,

a plurality of gate trenches extending from said top surface into said semiconductor substrate, said plurality of gate trenches forming zigzag patterns;

a contiguous formation of said plurality of gate trenches separating said plurality of source trenches from one another.

12. The power semiconductor device of claim 11, wherein at least one source contact is electrically coupled to said plurality of source regions.

13. The power semiconductor device of claim 11, wherein said plurality of source trenches are offset from one another.

14. The power semiconductor device of claim 11, further comprising a shallow p+ region adjacent to each of said plurality of source trenches.

15. A power semiconductor device comprising:

a plurality of source trenches adjacent to a plurality of source regions, said plurality of source trenches being offset from one another;

said plurality of source trenches extending from a top surface of a semiconductor substrate into said semiconductor substrate;

a plurality of gate trenches extending from said top surface into said semiconductor substrate;

a contiguous formation of said plurality of gate trenches separating said plurality of source trenches from one another.

16. The power semiconductor device of claim 15, wherein said plurality of gate trenches form hexagonal patterns.

17. The power semiconductor device of claim 15, wherein said plurality of gate trenches form zigzag patterns.

18. The power semiconductor device of claim 15, further comprising a shallow p+ region adjacent to each of said plurality of source trenches.

19. A semiconductor device comprising:

a plurality of shield electrode trenches, wherein each of said plurality of shield electrode trenches is substantially equally spaced from each adjacent shield electrode trench;

said plurality of shield electrode trenches extending from a top surface of a semiconductor substrate into said semiconductor substrate;

a respective shield electrode trench dielectric lining each of said plurality of shield electrode trenches;

a respective shield electrode adjacent said respective shield electrode trench dielectric and within each of said plurality of shield electrode trenches.

20. The semiconductor device of claim 19, further comprising a shallow p+ region adjacent to each of said plurality of shield electrode trenches.