FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE

• US 20140374841A1
• Filed: 09/11/2014
• Published: 12/25/2014
• Est. Priority Date: 10/31/2011
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wang, Chih-Jung, Chen, Tong-Yu
• Application Number:
  US14/483,165
• Publication Number:
  US 20140374841A1
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A FET with a fin structure includes a substrate, an isolation structure and a gate structure. The substrate includes at least one fin structure. The fin structure includes two source/drain regions and a gate channel region between the two source/drain regions. The isolation structure is disposed on the substrate and surrounds the fin structure to expose an upper portion of the fin structure. A width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region. A gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure is formed. Two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.

Claims

1. A field effect transistor with a fin structure comprising:

a substrate comprising at least one fin structure comprising two source/drain regions and a gate channel region between the two source/drain regions;

an isolation structure disposed on the substrate and surrounding the fin structure to expose an upper portion of the fin structure, wherein a width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region; and

a gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure, wherein two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.

2. The field effect transistor with a fin structure according to claim 1, further comprising a hard mask atop the gate channel region of the fin structure.

3. The field effect transistor with a fin structure according to claim 1, wherein the gate structure further covers a top of the gate channel region of the fin structure.

4. The field effect transistor with a fin structure according to claim 1, wherein the gate structure further covers the hard mask.