SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
First Claim
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1. A semiconductor package, comprising:
- a package substrate;
a first semiconductor chip on the package substrate; and
at least one second semiconductor chip on the first semiconductor chip and including bumps,wherein the bumps comprise memory I/O bumps and power/ground voltage bumps, and wherein the memory I/O bumps are adjacent to a center of the first semiconductor chip.
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Abstract
A semiconductor package includes memory I/O bumps and power/ground voltage bumps which are disposed at different positions from each other. In the semiconductor package, memory chips are disposed side by side, and a passivation layer is interposed between a conductive pad and a bump.
14 Citations
20 Claims
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1. A semiconductor package, comprising:
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a package substrate; a first semiconductor chip on the package substrate; and at least one second semiconductor chip on the first semiconductor chip and including bumps, wherein the bumps comprise memory I/O bumps and power/ground voltage bumps, and wherein the memory I/O bumps are adjacent to a center of the first semiconductor chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor package, comprising:
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a package substrate; a first semiconductor chip on the package substrate comprising first memory I/O bumps and first power/ground voltage bumps; and at least one second semiconductor chip on the first semiconductor chip and comprising second memory I/O bumps and second power/ground voltage bumps, wherein the first and second memory I/O bumps are adjacent to a center of the first semiconductor chip, and wherein the first and second power/ground voltage bumps are adjacent an edge region of at least one of the first semiconductor chip and the second semiconductor chip. - View Dependent Claims (17, 18, 19, 20)
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Specification