COMPONENT IN THE FORM OF A WAFER LEVEL PACKAGE AND METHOD FOR MANUFACTURING SAME

• US 20140374917A1
• Filed: 06/17/2014
• Published: 12/25/2014
• Est. Priority Date: 06/20/2013
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: WEBER, Heribert, KUEPPERS, Hartmut, Reutlingen, Jens, DAVIES, Neil
• Granted Patent: US 9,406,747 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the other; a molded upper sealing layer made of an electrically insulating casting; and an external electrical contacting of the component being implemented on the top side via at least one contact stamp which is embedded in the sealing layer so that (i) its lower end is connected to a wiring level of an element substrate and (ii) its upper end is exposed in the surface of the sealing layer.

Claims

1. A component in the form of a wafer level package, comprising:

at least two element substrates assembled one above the other;

a molded upper sealing layer of an electrically insulating casting compound; and

at least one contact stamp via which an external electrical contacting of the component on the top side of the component is implement, the at least one contact stamp being embedded in the molded upper sealing layer such that (i) a lower end of the at least one contact stamp is connected to a wiring level of one of the element substrates and (ii) an upper end of the at least one contact stamp is exposed on the surface of the sealing layer.

2. The component as recited in claim 1, wherein the at least one contact stamp contains at least one of Al, Cu, Au and Ag.

3. The component as recited in claim 1, wherein the at least one contact stamp is connected to a wiring level on the molded sealing layer, and wherein at least one terminal pad is formed in the wiring level on the molded sealing layer for external electrical contacting of the component.

4. The component as recited in claim 3, wherein at least one electrical connection in the form of a wire bond connection is implemented between active element front side of the two element substrates, and wherein the wire bond connection is completely embedded in the electrically insulating sealing layer.

5. The component as recited in claim 3, wherein at least one individual chip is assembled on the wafer level package, and wherein the at least one individual chip is at least partially embedded in the electrically insulating casting compound of the sealing layer.

6. A method for manufacturing a component in the form of a wafer level package, comprising:

processing at least two element substrates independently of one another to implement at least one of an electrical functionality and a micromechanical functionality for a plurality of components;

mechanically connecting the at least two element substrates to one another, in such a way that at least one contact surface of a wiring level of one of the at least two element substrates is exposed;

providing at least one electrical connection between the at least two element substrates;

providing at least one contact stamp on the at least one exposed contact surface of the wiring level of one of the at least two element substrates; and

molding an upper sealing layer of an electrically insulating casting compound to embed the at least one contact stamp in the molded upper sealing layer such that an upper end of the at least one contact stamp is exposed.

7. The method as recited in claim 6, wherein the at least one contact stamp is one of (i) positioned with the aid of a wire bonding machine or (ii) applied using an inkjet method.

8. The method as recited in claim 6, wherein the upper sealing layer is back-thinned to expose the upper end of the at least one contact stamp.

9. The method as recited in claim 6, wherein at least one rewiring level for the at least one contact stamp is provided on the upper sealing layer.

10. The method as recited in claim 6, wherein:

the at least two element substrates include an upper element substrate and a lower element substrate;

the upper element substrate is structured after being assembled on the lower element substrate to expose at least one contact area of the lower element substrate;

at least one wire bond connection is established between the at least one contact area of the lower element substrate and a wiring level of the upper element substrate; and

the at least one wire bond connection is completely embedded in the electrically insulating casting compound during molding of the sealing layer.

11. The method as recited in claim 10, wherein at least one individual chip is assembled on one of the at least two element substrates, the at least one individual chip being embedded at least partially in the electrically insulating casting compound during molding of the upper sealing layer.