TEMPORAL REDUNDANCY
First Claim
Patent Images
1. A circuit for coupling to a number of inter-chip communication channels, comprising:
- a first circuit to indicate whether at least one channel is faulty;
a second circuit to distribute data bits associated with a faulty channel to at least one non-faulty channel; and
a third circuit to generate a clock signal that clocks transmission of data bits to the communication channels, the clock signal being at an increased data rate when the first circuit indicates that at least one channel is faulty.
1 Assignment
0 Petitions
Accused Products
Abstract
A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.
-
Citations
23 Claims
-
1. A circuit for coupling to a number of inter-chip communication channels, comprising:
-
a first circuit to indicate whether at least one channel is faulty; a second circuit to distribute data bits associated with a faulty channel to at least one non-faulty channel; and a third circuit to generate a clock signal that clocks transmission of data bits to the communication channels, the clock signal being at an increased data rate when the first circuit indicates that at least one channel is faulty. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
8. A method, comprising:
-
receiving a first signal indicating at least one inter-chip communication channel is faulty; and transmitting data bits associated with a faulty channel and data bits associated with a non-faulty channel, via the non-faulty channel, at an increased data rate.
-
-
17. (canceled)
-
18. A memory controller, comprising:
-
a register to store information indicating a faulty communication channel; a first circuit to re-associate data bits originally associated with the faulty channel with one or more non-faulty channels; and a second circuit to generate a clock signal to facilitate transmission or receiving of the re-associated data bits via one or more non-faulty channels at an increased data rate. - View Dependent Claims (21, 22, 23)
-
-
19. (canceled)
-
20. (canceled)
Specification