128 Gigabit Fibre Channel Physical Architecture
First Claim
1. A physical layer network interface link apparatus comprising:
- a combined physical coding sublayer (PCS) and Reed-Solomon (RS) forward error correction (FEC) sublayer module, said combined PCS and RS FEC module developed on a single chip,wherein said combined PCS and RS FEC module includes;
a media access control (MAC) interface for connection to a MAC layer providing or receiving a stream of 64 bit blocks;
a physical media attachment (PMA) interface for connection to a PMA layer utilizing four lanes;
an RS FEC encoder module; and
an RS FEC decoder module, andwherein said combined PCS and RS FEC module operates using only four lanes.
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Accused Products
Abstract
The PCS and FEC layers are combined into a single layer and the number of lanes is set at four lanes. The combination allows removal of many modules as compared to a serial arrangement of a PCS layer and an FEC layer. The reduction in the number of lanes, as compared to 100 Gbps Ethernet, provides a further simplification or cost reduction by further reducing the needed gates of an ASIC to perform the functions. Changing the lanes in the FEC layer necessitates changing the alignment marker structure. In the preferred embodiment a lane zero marker is used as the first alignment marker in each lane to allow rapid sync. A second alignment marker indicating the particular lane follows the first alignment marker.
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Citations
18 Claims
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1. A physical layer network interface link apparatus comprising:
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a combined physical coding sublayer (PCS) and Reed-Solomon (RS) forward error correction (FEC) sublayer module, said combined PCS and RS FEC module developed on a single chip, wherein said combined PCS and RS FEC module includes; a media access control (MAC) interface for connection to a MAC layer providing or receiving a stream of 64 bit blocks; a physical media attachment (PMA) interface for connection to a PMA layer utilizing four lanes; an RS FEC encoder module; and an RS FEC decoder module, and wherein said combined PCS and RS FEC module operates using only four lanes. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A physical layer network interface link apparatus comprising:
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a media access control (MAC) layer having an interface providing or receiving a stream of 64 bit blocks; and a combined physical coding sublayer (PCS) and Reed-Solomon (RS) forward error correction (FEC) sublayer module, said combined PCS and RS FEC module developed on a single chip, wherein said combined PCS and RS FEC module includes; a MAC interface connected to said MAC layer interface; a physical media attachment (PMA) interface for connection to a PMA layer utilizing four lanes; an RS FEC encoder module; and an RS FEC decoder module, and wherein said combined PCS and RS FEC module operates using only four lanes. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A network switch comprising:
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a control processor; memory coupled to said control processor; and a switching system coupled to said control processor, said switching system including; a frame data storage system; a header processing system coupled to said frame data storage system; and a plurality of ports coupled to said frame data storage system, each of said plurality of ports including; a frame data storage system interface coupled to said frame data storage system; and a physical layer network interface link apparatus including; a media access control (MAC) layer having an interface providing or receiving a stream of 64 bit blocks; a combined physical coding sublayer (PCS) and Reed-Solomon (RS) forward error correction (FEC) sublayer module, said combined PCS and RS FEC module developed on a single chip; a physical media attachment (PMA) layer having an interface connected to said combined PCS and RS FEC module; and a physical media dependent (PMD) layer connected to said PMA layer and for connection to an external network link, wherein said combined PCS and RS FEC module includes; a MAC interface connected to said MAC layer interface; a PMA interface connected to said PMA layer interface utilizing four lanes; an RS FEC encoder module; and an RS FEC decoder module, and wherein said combined PCS and RS FEC module operates using only four lanes. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification