MAP RECYCLING ACCELERATION

• US 20140379959A1
• Filed: 07/15/2013
• Published: 12/25/2014
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Canepa, Timothy, Baryudin, Leonid, Hanna, Stephen D., Tang, Alex G.
• Granted Patent: US 9,405,672 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile. The circuit is generally configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in the memory and (ii) notify the processor in response to a detection in the first level of one or more of the source blocks to be recycled that contain valid data.

Claims

1. An apparatus comprising:

a processor configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile; and

a circuit configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in said memory and (ii) notify said processor in response to a detection in said first level of one or more of said source blocks to be recycled that contain valid data.

2. The apparatus according to claim 1, wherein said processor is further configured to recycle said map in response to said notification.

3. The apparatus according to claim 2, wherein said searching of said first level is implemented in dedicated hardware to accelerate said recycling of said map.

4. The apparatus according to claim 1, wherein said operation (i) moves said valid data from said source blocks to one or more destination blocks in said memory and (ii) updates said map.

5. The apparatus according to claim 1, wherein (i) said circuit is further configured to lock one or more slots in a plurality of second levels of said map during said operation to prevent changes to said first level of said map and (ii) said slots correspond to said source blocks to be recycled.

6. The apparatus according to claim 1, wherein said circuit is further configured to suspend said operation while servicing a new command from said computer to access said translations to said memory.

7. The apparatus according to claim 1, wherein said processor is further configured to copy a second of said levels of said map to said memory in response to said detection of said source blocks to be recycled that contain valid data.

8. The apparatus according to claim 1, wherein said detection of said valid data is performed independently of a plurality of headers in said source blocks.

9. The apparatus according to claim 1, wherein said apparatus is implemented in a solid-state drive.

10. The apparatus according to claim 1, wherein said apparatus is implemented as one or more integrated circuits.

11. A method for map recycling acceleration, comprising the steps of:

(A) initiating an operation to recycle a plurality of source blocks in a memory that is nonvolatile;

(B) searching through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in said memory; and

(C) notifying a processor in response to a detection in said first level of one or more of said source blocks to be recycled that contain valid data.

12. The method according to claim 11, further comprising the step of:

recycling said map using said processor in response to said notification.

13. The method according to claim 12, wherein said searching of said first level is implemented in dedicated hardware to accelerate said recycling of said map.

14. The method according to claim 11, wherein said operation (i) moves said valid data from said source blocks to one or more destination blocks in said memory and (ii) updates said map.

15. The method according to claim 11, further comprising the step of:

locking one or more slots in a plurality of second levels of said map during said operation to prevent changes to said first level of said map, wherein said slots correspond to said source blocks to be recycled.

16. The method according to claim 11, further comprising the step of:

suspending said operation while servicing a new command from said computer to access said translations to said memory.

17. The method according to claim 11, further comprising the step of:

copying a second of said levels of said map to said memory in response to said detection of said source blocks to be recycled that contain valid data.

18. The method according to claim 11, wherein said detection of said valid data is performed independently of a plurality of headers in said source blocks.

19. The method according to claim 11, wherein said method is implemented in a solid-state drive.

20. An apparatus comprising:

means for initiating an operation to recycle a plurality of source blocks in a memory that is nonvolatile;

means for searching through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in said memory; and

means for notifying in response to a detection in said first level of one or more of said source blocks to be recycled that contain valid data.