DEPENDENT INSTRUCTION SUPPRESSION

• US 20140380024A1
• Filed: 06/25/2013
• Published: 12/25/2014
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Spadini, Francesco, Achenbach, Michael
• Granted Patent: US 9,715,389 B2
• Time in Patent Office: Days
• US Class Current: 712/217
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A method includes suppressing execution of at least one dependent instruction of a load instruction by a processor using stored dependency information responsive to an invalid status of the load instruction. A processor includes an execution unit to execute instructions and a scheduler. The scheduler is to select for execution in the execution unit a load instruction having at least one dependent instruction and suppress execution of the at least one dependent instruction using stored dependency information responsive to an invalid status of the load instruction.

Claims

1. A method comprising:

suppressing execution of at least one dependent instruction of a load instruction by a processor using stored dependency information responsive to an invalid status of the load instruction.

2. The method of claim 1, further comprising waking the at least one dependent instruction responsive to scheduling the load instruction for execution.

3. The method of claim 2, wherein waking the at least one dependent instruction further comprises setting a status indicator of the at least one dependent instruction to awake and suppressing execution of the at least one dependent instruction further comprises setting the status indicator to sleep.

4. The method of claim 2, wherein waking the at least one dependent instruction further comprises:

comparing a first register name referenced by the load instruction to a second register name referenced by the at least one dependent instruction; and

waking the at least one dependent instruction responsive to the first register name matching the second register name.

5. The method of claim 1, further comprising storing the dependency information in an entry of a scheduler queue for the at least one dependent instruction, wherein a dependency relationship between the load instruction and the at least one dependent instruction covers one or more levels of dependency.

6. The method of claim 2, wherein the dependency information comprises a replay tag associated with the load instruction, further comprising:

assigning the replay tag to the load instruction; and

assigning the replay tag to the at least one dependent instruction.

7. The method of claim 6, further comprising:

waking a second instruction responsive to waking the at least one dependent instruction, the second instruction being dependent on the at least one dependent instruction;

assigning the replay tag to the second instruction; and

suppressing execution of the second instruction responsive to the indication of the invalid status based on the replay tag.

8. The method of claim 5, wherein the dependency information comprises a plurality of bits associated with entries in the scheduler queue other than the entry for the at least one dependent instruction, and a bit of the plurality of bits corresponding to an entry in the scheduler queue for the load instruction is set in the dependency information.

9. The method of claim 1, wherein suppressing execution of the at least one dependent instruction comprises terminating execution of the at least one dependent instruction.

10. A method comprising:

storing dependency information identifying a dependency relationship between a load instruction and at least one dependent instruction, wherein the dependency relationship covers one or more levels of dependency;

scheduling the load instruction for execution by a processor;

waking the at least one dependent instruction;

receiving indication of an invalid status of the load instruction; and

suppressing execution of the least one dependent instruction by the processor responsive to the indication of the invalid status based on the dependency information.

11. The method of claim 10, wherein the dependency information comprises a replay tag associated with the load instruction, further comprising:

assigning the replay tag to the load instruction; and

assigning the replay tag to the at least one dependent instruction.

12. The method of claim 11, further comprising:

waking a second instruction responsive to waking the at least one dependent instruction, the second instruction being dependent on the at least one dependent instruction;

assigning the replay tag to the second instruction; and

suppressing execution of the second instruction responsive to the indication of the invalid status based on the replay tag.

13. The method of claim 10, wherein the dependency information comprises a plurality of bits associated with entries in a scheduler queue other than an entry for the at least one dependent instruction, and a bit of the plurality of bits corresponding to an entry in the scheduler queue for the load instruction is set in the dependency information.

14. A processor comprising:

an instruction pipeline, comprising;

an execution unit to execute instructions; and

a scheduler to select for execution in the execution unit a load instruction having at least one dependent instruction and suppress execution of the at least one dependent instruction using stored dependency information responsive to an invalid status of the load instruction.

15. The processor of claim 14, wherein the scheduler is to awake the at least one dependent instruction responsive to scheduling the load instruction for execution.

16. The processor of claim 15, wherein the scheduler is to waking the at least one dependent instruction by setting a status indicator of the at least one dependent instruction to awake and suppressing execution of the at least one dependent instruction by setting the status indicator to sleep.

17. The processor of claim 15, wherein the scheduler is to awake the at least one dependent instruction by comparing a first register name referenced by the load instruction to a second register name referenced by the at least one dependent instruction and waking the at least one dependent instruction responsive to the first register name matching the second register name.

18. The processor of claim 14, wherein the scheduler comprises a scheduler queue and the scheduler is to store the dependency information in an entry of the scheduler queue for the at least one dependent instruction, wherein a dependency relationship between the load instruction and the at least one dependent instruction covers one or more levels of dependency.

19. The processor of claim 18, wherein the dependency information comprises a replay tag associated with the load instruction, and the scheduler is to assign the replay tag to the load instruction and assign the replay tag to the at least one dependent instruction.

20. The processor of claim 19, wherein the scheduler is to awake a second instruction responsive to waking the at least one dependent instruction, the second instruction being dependent on the at least one dependent instruction, assign the replay tag to the second instruction, and suppress execution of the second instruction responsive to the indication of the invalid status based on the replay tag.

21. The processor of claim 18, wherein the dependency information comprises a plurality of bits associated with entries in the scheduler queue other than the entry for the at least one dependent instruction, and the scheduler is to set a bit of the plurality of bits corresponding to an entry in the scheduler queue for the load instruction.

22. The processor of claim 14, wherein the scheduler is to suppress execution of the at least one dependent instruction by informing the execution unit to terminate execution of the at least one dependent instruction.