MANAGEMENT OF HARDWARE ACCELERATOR CONFIGURATIONS IN A PROCESSOR CHIP
First Claim
1. In a processor having one or more programmable logic circuits, a method to implement an accelerator program in one of the one or more programmable logic circuits, the method comprising:
- monitoring a use state of the processor as instructions of an application are being executed by the processor;
selecting an accelerator program stored in a library associated with the processor based on the use state of the processor; and
programming the one of the one or more programmable logic circuits with the selected accelerator programwherein selecting the accelerator program stored in the library comprises selecting the accelerator program based on the use state of the processor comprising at least one of current time of day, current physical location of the processor, availability of external power, remaining battery charge, and power use associated with one or more applications running on the processor.
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Accused Products
Abstract
Techniques described herein generally include methods for the management of hardware accelerator images in a processor chip that includes one or more programmable logic circuits. Hardware accelerator images may be optimized by swapping out which hardware accelerator images are implemented in the one or more programmable logic circuits. The hardware accelerator images may be chosen from a library of accelerator programs downloaded to a device associated with the processor chip. Furthermore, the specific hardware accelerator images that are implemented in the one or more programmable logic circuits at a particular time may be selected based on which combination of accelerator images best enhances performance and power usage of the processor chip.
57 Citations
35 Claims
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1. In a processor having one or more programmable logic circuits, a method to implement an accelerator program in one of the one or more programmable logic circuits, the method comprising:
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monitoring a use state of the processor as instructions of an application are being executed by the processor; selecting an accelerator program stored in a library associated with the processor based on the use state of the processor; and programming the one of the one or more programmable logic circuits with the selected accelerator program wherein selecting the accelerator program stored in the library comprises selecting the accelerator program based on the use state of the processor comprising at least one of current time of day, current physical location of the processor, availability of external power, remaining battery charge, and power use associated with one or more applications running on the processor. - View Dependent Claims (3, 4, 5, 6, 7)
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2. (canceled)
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8. A method to program a programmable logic circuit in a processor, the method comprising:
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monitoring use of a programmable logic circuit when the programmable logic circuit in the processor is programmed with a first accelerator program; recording data associated with use of the programmable logic circuit when the programmable logic circuit is programmed with the first accelerator program; selecting a second accelerator program based on the recorded data; retrieving the second selected accelerator program from a library associated with the processor; and programming the programmable logic circuit in the processor with the second accelerator program. - View Dependent Claims (9, 10, 11, 12, 13)
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14. In a processor having one or more programmable logic circuits, a method to program a programmable logic circuit, the method comprising:
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determining a first power cost associated with reprogramming one of the one or more programmable logic circuits with an accelerator program configured to run a portion of an application, and running the application with the reprogrammed logic circuit; determining a second power cost associated with running the application without using the reprogrammed logic circuit; comparing the first power cost to the second power cost; and based on the comparison, programming the one of the one or more programmable logic circuits with the accelerator program configured to run the portion of the application. - View Dependent Claims (15, 16, 17)
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18. A processor comprising:
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one or more programmable logic circuits; a non-volatile memory; and a strategy module configured to; store in the non-volatile memory one or more accelerator programs for the one or more programmable logic circuits; monitor energy usage of the one or more programmable logic circuits; and based on the monitored energy usage, program the one or more programmable logic circuits with the stored one or more accelerator programs. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. In a processor having one or more programmable logic circuits and a non-volatile memory, a method to program the one or more programmable logic circuits, the method comprising:
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storing in the non-volatile memory one or more accelerator programs for the one or more programmable logic circuits; monitoring energy usage of the one or more programmable logic circuits; and based on monitored energy usage, programming the one or more programmable logic circuits with the stored one or more accelerator programs. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35)
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Specification