MACHINE CHECK ARCHITECTURE EXECUTION ENVIRONMENT FOR NON-MICROCODED PROCESSOR

• US 20140380085A1
• Filed: 06/23/2013
• Published: 12/25/2014
• Est. Priority Date: 06/23/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hinton, Glenn J., Rash, Willam C., Hanh, Scott D.
• Granted Patent: US 9,141,461 B2
• Time in Patent Office: Days
• US Class Current: 714/3
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G06F 11/142 Reconfiguring to eliminate the error group management mechanisms in a peer-to-peer network H04L67/1044
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 2201/815 Virtual

Abstract

A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.

Claims

1. An apparatus comprising:

a memory comprising a dedicated memory portion for an error monitoring state;

a non-microcoded processing device coupled to the memory, the non-microcoded processing device to;

obtain an occurrence of an error, the occurrence of the error causing the non-microcoded processing device to enter the error monitoring state;

process the error using the dedicated memory portion while the non-microcoded processing device is in the error monitoring state, wherein the error monitoring state is dedicated to error processing; and

determine information associated with the error, wherein the information associated with the error is in a predefined format.

2. The apparatus of claim 1, wherein to process the error in the error monitoring state, the non-microcoded processing device is to:

upon obtaining a fault, suppress the fault;

upon obtaining an additional error, mask the additional error; and

allow a security policy associated with the processing device to be violated.

3. The apparatus of claim 2,

wherein to suppress the fault, the non-microcoded processing device sets a fault suppress flag,

wherein to mask the additional error, the non-microcoded processing device sets an error suppress flag,

wherein to allow a security policy to be violated, the non-microcoded processing device sets a security policy violation flag, and

wherein the non-microcoded processing device accesses at least one of the fault suppress flag, the error suppress flag, or the security policy violation flag to avoid causing additional errors.

4. The apparatus of claim 1, wherein to determine information associated with the error, the non-microcoded processing device is to:

initiate a test by a hardware state machine, wherein the hardware state machine is dedicated to the error monitoring state and cannot be initiated in an execution state other than the error monitoring state; and

obtain data based on the test by the hardware state machine.

5. The apparatus of claim 1, wherein to process the error in the error monitoring state, the non-microcoded processing device is to:

upon determining that another processing device should not execute instructions, instruct the another processing device to perform at least one of;

stop executing instructions, report status, or wait for resolution.

6. The apparatus of claim 1, wherein to process the error in the error monitoring state, the non-microcoded processing device is to:

send a coherency message to another processing device, where the another processing device is in an execution state other than the error monitoring state.

7. The apparatus of claim 1, further comprising a severity register indicating a severity of the error, wherein the severity register is accessible only when the non-microcoded processing device is in the error monitoring state.

8. The apparatus of claim 1, wherein the non-microcoded processing device is further to prevent another processing device from modifying the dedicated memory portion for the error monitoring state.

9. The apparatus of claim 1, wherein the non-microcoded processing device is further to:

cause a hardware operation to be performed to test operation of hardware associated with the apparatus; and

obtain a result of the hardware operation as the information associated with the error.

10. The apparatus of claim 1, wherein the non-microcoded processing device is further to:

store the information associated with the error in a data structure in a portion of the memory dedicated to a machine check architecture.

11. The apparatus of claim 1, wherein the non-microcoded processing device is further to:

determine whether to resume execution of an application that was interrupted based on the occurrence of the error;

upon determining to resume execution of the application that was interrupted based on the occurrence of the error, cause the execution of the application to resume;

upon determining not to resume execution of the application that was interrupted based on the occurrence of the error, determine if the apparatus can recover from the occurrence of the error;

upon determining that the apparatus can recover from the occurrence of the error, pass control to an operating system to handle the error; and

upon determining that the apparatus cannot recover from the occurrence of the error, force a reset of the apparatus.

12. A method for building a virtual device, the method comprising:

obtaining an occurrence of an error, the occurrence of the error causing a non-microcoded processing device to enter an error monitoring state;

processing, by the non-microcoded processing device, the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state, wherein the error monitoring state is dedicated to error processing; and

determining information associated with the error, wherein the information associated with the error is in a predefined format.

13. The method of claim 12, wherein processing the error in the error monitoring state comprises:

upon obtaining a fault, suppressing the fault;

upon obtaining an additional error, masking the additional error; and

allowing a security policy associated with the processing device to be violated.

14. The method of claim 12,

wherein suppressing the fault comprises setting a fault suppress flag,

wherein masking the additional error comprises setting an error suppress flag,

wherein allowing a security policy to be violated comprises setting a security policy violation flag, and

wherein the method further comprises accessing at least one of the fault suppress flag, the error suppress flag, or the security policy violation flag to avoid causing additional errors.

15. The method of claim 12, wherein determining information associated with the error comprises:

initiating a test by a hardware state machine, wherein the hardware state machine is dedicated to the error monitoring state and cannot be initiated in the first state; and

obtaining data based on the test by the hardware state machine.

16. The method of claim 12, wherein processing the error in the error monitoring state comprises:

upon determining that another processing device should not execute instructions, instructing the another processing device to perform at least one of;

stop executing instructions, report status, or wait for resolution;

sending a coherency message to another processing device, where the another processing device is in an execution state other than the error monitoring state; and

preventing another processing device from modifying the dedicated memory portion.

17. The method of claim 12, further comprising:

causing a hardware operation to be performed to test operation of hardware associated with the error; and

obtaining a result of the hardware operation as the information associated with the error.

18. A non-transitory machine-readable storage medium including instructions that, when executed by a non-microcoded processing device, cause the non-microcoded processing device to perform operations comprising:

obtain an occurrence of an error, the occurrence of the error causing the non-microcoded processing device to enter an error monitoring state;

process the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state, wherein the error monitoring state is dedicated to error processing; and

determine information associated with the error, wherein the information associated with the error is in a predefined format.

19. The non-transitory machine-readable storage medium of claim 18, wherein the operations further comprise:

sending a resume message to another processing device to cause the another processing device to resume execution in an execution state other than the error monitoring state.

20. The non-transitory machine-readable storage medium of claim 18, wherein the operations further comprise:

determining whether to resume execution of an application that was interrupted based on the occurrence of the error;

upon determining to resume execution of the application that was interrupted based on the occurrence of the error, causing the execution of the application to resume;

upon determining not to resume execution of the application that was interrupted based on the occurrence of the error, determining if a computing system associated with the error can recover from the occurrence of the error;

upon determining that the computing system can recover from the occurrence of the error, passing control to an operating system to handle the error; and

upon determining that the computing system cannot recover from the occurrence of the error, forcing a reset of the computing system.