MEMORY SYSTEM AND METHOD OF READING DATA THEREOF

• US 20140380129A1
• Filed: 06/23/2014
• Published: 12/25/2014
• Est. Priority Date: 06/24/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SHIN, HYUN-HO, LIM, HEUNG-SOO
• Granted Patent: US 9,478,298 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Provided is a method of reading data in a memory system including a non-volatile memory device. The method includes reading first data stored in a first block using a first read scheme capable of detecting/correcting an error in the first data, and upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block and reading second data stored in the first temporary bad block using a second read scheme different from the first read scheme.

Claims

1. A method of reading data in a memory system including a non-volatile memory device, the method comprising:

reading first data stored in a first block of the non-volatile memory device using a first read scheme in response to a first read command, wherein the first read scheme is capable of detecting/correcting an error in the first data;

upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block, and reading second data stored in the first temporary bad block using a second read scheme different from the first read scheme in response to a second read command, wherein the second read scheme is capable of detecting/correcting an error in the second data; and

upon determining an uncorrected error in the second data, setting the first temporary bad block as a bad block.

2. The method of claim 1, wherein the first read scheme is a hard decision scheme, and the second read scheme is a soft decision scheme.

3. The method of claim 1, further comprising:

programming write data to the first temporary bad block only if a given percentage of the total data storage capacity of the non-volatile memory device is exceeded.

4. The method of claim 1, further comprising:

reading the first read data from the first temporary bad block only if a given percentage of the total data storage capacity of the non-volatile memory device is exceeded.

5. The method of claim 1, further comprising:

correcting an error in the second data using the second read scheme, and programming the corrected second data to the first temporary bad block; and

reading the corrected second read data from the first temporary bad block only if a given percentage of the total data storage capacity of the non-volatile memory device is exceeded.

6. The method of claim 1, further comprising:

correcting an error in the second data using the second read scheme; and

thereafter,

copying the corrected second read data from the first block to a normal second block.

7. The method of claim 5, further comprising reading the data stored in the second block, in response to a second read command about the data stored in the first block set as the first temporary bad block.

8. The method of claim 1, wherein in response to a second read command about the data stored in the first block set as the first temporary bad block, the data stored in the first block is read by the second scheme without reading the data stored in the first block by the first scheme.

9. A method of operating a memory system including a non-volatile memory device divided into memory blocks, the method comprising:

using different read schemes to assign each memory block one of a range of read/write block designation levels; and

thereafter,

programming write data to each memory block in accordance with an assigned one of the read/write designation levels.

10. The method of claim 9, wherein using the different read schemes to assign each memory block one of a range of read/write block designation levels comprises:

reading first data stored in a first block of the non-volatile memory device using a first read scheme, wherein the first read scheme is capable of detecting/correcting an error in the first data;

upon determining an uncorrected error in the first data after reading the first read data using the first read scheme, setting the first block as a first temporary bad block; and

thereafter,

reading second data stored in the first temporary bad block using a second read scheme different from the first read scheme, wherein the second read scheme is capable of detecting/correcting an error in the second data; and

upon determining an uncorrected error in the second data, setting the first temporary bad block as a second temporary bad block.

11. The method of claim 10, wherein the first read scheme is a hard decision scheme, and the second read scheme is a soft decision scheme.

12. The method of claim 10, further comprising:

programming write data to the first temporary bad block only if a first percentage of the total data storage capacity of the non-volatile memory device is exceeded; and

programming write data to the second temporary bad block only if a second percentage higher than the first percentage of the total data storage capacity of the non-volatile memory device is exceeded.

13. The method of claim 10, further comprising:

correcting an error in the second data using the second read scheme; and

thereafter,

copying the corrected second read data from the first block to a normal second block.

14. A memory system comprising:

a non-volatile memory cell array including memory blocks that store data; and

a memory controller configured to control operation of the non-volatile memory cell array,

wherein the memory controller is configured to read first data stored in a first block of the non-volatile memory device using a first read scheme the first read scheme being capable of detecting/correcting an error in the first data, and upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block, and

the memory controller is further configured to read second data stored in the first temporary bad block using a second read scheme different from the first read scheme, the second read scheme being capable of detecting/correcting an error in the second data.

15. The memory system of claim 14, wherein the first read scheme is a hard decision scheme, and the second read scheme is a soft decision scheme.

16. The memory system of claim 14, wherein the memory controller is further configure to program write data to the first temporary bad block only if a given percentage of the total data storage capacity of the non-volatile memory device is exceeded.

17. The memory system of claim 14, wherein the memory controller is further configured to read the first read data from the first temporary bad block only if a given percentage of the total data storage capacity of the non-volatile memory device is exceeded.

18. The memory system of claim 14, wherein the memory controller is further configured to correct an error in the second data using the second read scheme, program the corrected second data to the first temporary bad block, and read the corrected second read data from the first temporary bad block only if a given percentage of the total data storage capacity of the non-volatile memory device is exceeded.

19. The memory system of claim 14, wherein the memory controller is further configured to correct an error in the second data using the second read scheme, and thereafter, copy the corrected second read data from the first block to a normal second block.

20. The memory system of claim 14, wherein the non-volatile memory device is a NAND flash memory device.