Systems and Methods of Detecting Power Bugs

• US 20140380283A1
• Filed: 06/24/2014
• Published: 12/25/2014
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Purdue Research Foundation (The Trustees of Purdue University (d/b/a Purdue University))
• Original Assignee: Purdue Research Foundation (The Trustees of Purdue University (d/b/a Purdue University))
• Inventors: Hu, Yu Charlie, Pathak, Abhinav, Jindal, Abhilash, Midkiff, Samuel
• Granted Patent: US 9,501,382 B2
• Time in Patent Office: Days
• US Class Current: 717/132
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/0742 in a data processing system embedded in a mobile device, e.g. mobile phones, handheld devices
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3604 Software analysis for verifying properties of programs byte-code verification G06F9/44589
• CPC Class Codes: G06F 11/3608 using formal methods, e.g. model checking, abstract interpretation theorem proving G06N5/013
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 8/20 Software design
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis

Abstract

Embodiments of the present invention provide a system and methods for detecting power bugs. In one embodiment, a computer-implemented method for analyzing a computer code includes generating a control flow graph for at least a portion of the computer code at a processor. The method further includes identifying power bugs by traversing the control flow graph if the control flow graph exits without performing a function call to deactivate power to any component of a device configured to execute computer executable instructions based on the computer code after performing a function call to activate power.

Claims

1. A computer-implemented method for analyzing a computer code, the method comprising:

at a processor, generating a control flow graph for at least a portion of the computer code; and

identifying power bugs by traversing the control flow graph to identify if the control flow graph exits without performing a function call to deactivate power to any component of a device configured to execute computer executable instructions based on the computer code after performing a function call to activate power.

2. The method of claim 1, further comprising generating an error message if the control flow graph exits without performing a function call to deactivate power to any component.

3. The method of claim 2, further comprising storing the error message in a non-transitory memory medium.

4. The method of claim 1, wherein the computer executable instructions are configured to run on a power constrained device.

5. The method of claim 4, wherein the function call to activate power comprises a function call to prevent the power constrained device from going to sleep, and wherein the function call to deactivate power comprises a function call to re-allow the power constrained device to go to sleep.

6. The method of claim 4, further comprising:

receiving the computer code; and

removing the identified power bugs.

7. The method of claim 6, further comprising:

after removing the identified power bugs, generating the computer executable instructions by compiling the computer code if the computer code exits after performing a function call to deactivate power to any component previously activated; and

storing the computer executable instructions in a non-transitory memory medium.

8. The method of claim 7, further comprising:

providing an application comprising the computer executable instructions to a user device at an online market place.

9. The method of claim 1, wherein identifying power bugs comprises applying a forward dataflow analysis.

10. The method of claim 9, wherein applying the forward dataflow analysis comprises applying a reaching definitions analysis to identify any mismatch in definitions relating to function calls for activating or deactivating power.

11. The method of claim 10, wherein applying the reaching definitions analysis comprises:

identifying steps in the control flow graph relating to function calls for activating or deactivating power;

defining a power variable for each step with a function call for activation and for each step with a function call for deactivation that are identified;

assigning a first binary value to the power variable for each function call for activation and assigning an opposite second binary value to the power variable for each function call for deactivation;

generating a set of definitions of the power variable reaching an EXIT block of the control flow graph; and

identifying a power bug if any definition of the first binary value is identified in the set of definitions of the power variable at the EXIT block.

12. The method of claim 9, wherein applying the forward dataflow analysis comprises applying a live variable analysis, or an available expressions analysis.

13. The method of claim 1, wherein identifying power bugs comprises applying a backward dataflow analysis.

14. The method of claim 1, wherein the computer code is configured to execute as a single thread process.

15. The method of claim 1, wherein generating the control flow graph comprises:

generating individual control flow graph for each event handler in the computer code comprising a plurality of event handlers; and

stitching together the individual control flow graphs.

16. The method of claim 1, wherein computer code is configured to execute as a multi-threaded application.

17. The method of claim 16, wherein generating the control flow graph comprises generating a control flow graph for a multi-threaded application.

18. The method of claim 17, wherein generating the control flow graph comprises:

generating individual control flow graph for each thread;

connecting a fork spawning each thread with an ENTRY block of the individual control flow graph for that thread; and

connecting an EXIT block of the individual control flow graph for that thread with a join node or with another ENTRY block of another individual control flow graph of another thread.

19. A computing device comprising:

a processor configured to execute a debugging tool, the debugging tool configured to;

generate a control flow graph for at least a portion of a computer code, and

identify power bugs by detecting if the control flow graph exits without performing a function call for deactivating power to any component of a device configured to execute computer executable instructions based on the computer code by traversing the control flow graph after performing a function call to activate power.

20. A non-transitory storage medium comprising a debugging tool, the debugging tool configured to analyze a computer code by:

generating a control flow graph for at least a portion of the computer code; and

identifying power bugs by detecting if the control flow graph exits without performing a function call for deactivating power to any component of a device configured to execute computer executable instructions based on the computer code by traversing the control flow graph after performing a function call to activate power.