SYSTEMS AND METHODS FOR PROCEDURE RETURN ADDRESS VERIFICATION

• US 20140380468A1
• Filed: 06/23/2013
• Published: 12/25/2014
• Est. Priority Date: 06/23/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Gideon Gerzon, Jared W. Stark
• Inventors: GERZON, GIDEON, STARK, JARED W., DISKIN, GAL
• Granted Patent: US 9,015,835 B2
• Time in Patent Office: Days
• US Class Current: 726/22
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow

Abstract

An example processing system may comprise: a stack pointer configured to reference a first return address stored on a stack; a return address buffer pointer configured to reference a second return address stored in a return address buffer; and a return address verification logic configured, responsive to receiving a return instruction, to compare the first return address to the second return address.

Claims

1. A processing system, comprising:

a stack pointer configured to reference a first return address stored on a stack;

a return address buffer pointer configured to reference a second return address stored in a return address buffer; and

a return address verification logic configured, responsive to receiving a return instruction, to compare the first return address to the second return address.

2. The processing system of claim 1, wherein the return address verification logic is further configured to execute the return instruction responsive to determining that the first return address is equal to the second return address.

3. The processing system of claim 1, wherein the return address verification logic is further configured to generate a stack fault exception responsive to determining that the first return address differs from the second return address.

4. The processing system of claim 1, wherein the return address verification logic is further configured, responsive to receiving a call instruction, to store a return address on the stack and in the return address buffer.

5. The processing system of claim 1, wherein the return address verification logic is further configured, responsive to receiving a return address buffer modification instruction, to perform at least one of:

storing a return address in the return address buffer or removing a return address from the return address buffer.

6. The processing system of claim 5, wherein the return address buffer modification instruction is a privileged instruction.

7. The processing system of claim 1, wherein the return address verification logic is further configured, responsive to receiving a return address buffer pointer modification instruction, to perform at least one of:

increment the return address buffer pointer or decrement the return address buffer pointer.

8. The processing system of claim 7, wherein the return address buffer pointer modification instruction is a privileged instruction.

9. The processing system of claim 1, wherein the stack is residing within a memory communicatively coupled to the processing system.

10. The processing system of claim 1, wherein the return address buffer is at least partially residing within a memory incorporated into the processing system.

11. The processing system of claim 1, wherein the return address buffer comprises a first portion residing within a memory incorporated into the processing system and a second portion residing within an external memory.

12. The processing system of claim 11, wherein the external memory is provided by a read-only memory.

13. The processing system of claim 11, wherein the second portion is configured to operate as an overflow buffer relatively to the first portion.

14. A method, comprising:

modifying, by a processing system, a stack pointer;

modifying a return address buffer pointer;

receiving a return instruction;

comparing a first return address referenced by the stack pointer to a second return address referenced by the return address buffer pointer; and

executing the return instruction responsive to determining that the first return address is equal to the second return address.

15. The method of claim 14, further comprising generating a stack fault exception responsive to determining that the first return address differs from the second return address.

16. The method of claim 14, further comprising storing a return address on the stack and in the return address buffer responsive to receiving a call instruction.

17. The method of claim 14, further comprising:

receiving a return address buffer modification instruction; and

performing at least one of;

storing a return address in the return address buffer or removing a return address from the return address buffer.

18. The method of claim 14, further comprising:

initializing the return address buffer pointer to point to an internal return address buffer;

modifying the return address buffer pointer;

determining that a boundary of the internal return address buffer is reached; and

causing the return address buffer pointer to point to an external return address buffer.

19. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing system, cause the processing system to perform operations, comprising:

modifying a stack pointer;

modifying a return address buffer pointer;

receiving a return instruction;

comparing a first return address referenced by the stack pointer to a second return address referenced by a return address buffer pointer; and

executing the return instruction responsive to determining that the first return address is equal to the second return address.

20. The computer-readable non-transitory storage medium of claim 19, further comprising executable instructions causing the processing system to generate a stack fault exception responsive to determining that the first return address differs from the second return address.