SEMICONDUCTOR DEVICE

• US 20150001460A1
• Filed: 04/22/2014
• Published: 01/01/2015
• Est. Priority Date: 06/27/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hyunchul Back, Jin-Soo Lim, Kwang Soo Seol, Seong-Soon Cho, Taekyung Kim
• Inventors: SEOL, KWANG SOO, LIM, Jin-Soo, CHO, SEONG SOON, KIM, TAEKYUNG, BACK, HYUNCHUL
• Granted Patent: US 9,553,101 B2
• Time in Patent Office: Days
• US Class Current: 257/5
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 51/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/25 based on bulk electronic defects, e.g. trapping of electrons
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: H10N 70/884 : Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.

Claims

1. A semiconductor device comprising:

a plurality of gate structures spaced apart above a top surface of a substrate, the plurality of gate structures including a horizontal electrode extending in a first direction parallel with the top surface of the substrate;

an isolation insulating material disposed between the gate structures; and

a plurality of cell pillars penetrating the horizontal electrode and connected to the substrate,

wherein a thickness of the horizontal electrode is greater than a first spacing defined by a shortest distance between any two of the plurality of the cell pillars.

2. The semiconductor device of claim 1, wherein the thickness of the horizontal electrode is greater than a second spacing of the cell pillars defined by a shortest distance between two adjacent cell pillars of the plurality of cell pillars that are nearest to the isolation insulating material.

3. The semiconductor device of claim 2, wherein the second spacing of the cell pillars is greater than the first spacing of the cell pillars.

4. The semiconductor device of claim 1, wherein the plurality of cell pillars includes first cell pillars nearest to the isolation insulating material and second cell pillars next nearest to the isolation insulating material.

5. The semiconductor device of claim 4, wherein the first cell pillars and the second cell pillars are arranged in a zigzag.

6. The semiconductor device of claim 4, wherein a distance between a pair of immediately adjacent first cell pillars is equal to or greater than a distance between a pair of immediately adjacent second cell pillars.

7. The semiconductor device of claim 4, wherein a diameter of a first cell pillar is less than a diameter of a second cell pillar.

8. The semiconductor device of claim 6, wherein the distance between the pair of immediately adjacent first cell pillars is greater than a distance between one of the first cell pillars and one of the second cell pillars nearest to the one of the first cell pillars.

9. The semiconductor device of claim 4, wherein the plurality of cell pillars further includes third cell pillars third-nearest to the isolation insulating material;

and

wherein the first to third cell pillars are arranged in a zigzag.

10. The semiconductor device of claim 9, wherein a distance between one of the second cell pillars and one of the first cell pillars nearest thereto is greater than a distance between one of the second cell pillars and one of the third cell pillars nearest thereto.

11. A semiconductor device comprising:

gate structures disposed above a substrate, each of the gate structures including vertically stacked horizontal electrodes and insulating patterns between the horizontal electrodes;

a first isolation insulating layer disposed between the gate structures; and

a plurality of cell pillars penetrating the gate structures and connected to the substrate,

wherein a thickness of each of the horizontal electrodes in the gate structures is greater than a distance between adjacent cell pillars where the cell pillars penetrate the horizontal electrode.

12. The semiconductor device of claim 11, wherein each of the gate structures includes horizontally spaced apart first and second uppermost horizontal electrodes.

13. The semiconductor device of claim 12, further comprising:

a second isolation insulating layer filling a trench between the first and second uppermost horizontal electrodes, the trench extending from a top surface of the gate structure to the substrate through the vertically stacked horizontal electrodes.

14. The semiconductor device of claim 13, wherein the trench is provided between cell pillars in a center portion of each of the gate structures;

and

wherein a distance between the second isolation insulating layer and a cell pillar nearest to the second isolation insulating layer is less than a distance between a pair of immediately adjacent cell pillars.

15. The semiconductor device of claim 12, further comprising:

dummy pillars extending to the substrate through the gate structures between the horizontally spaced apart first and second uppermost horizontal electrodes.

16. The semiconductor device of claim 15, wherein the dummy pillars are disposed between the cell pillars in a center portion of each of the gate structures;

and

wherein the dummy pillars and the cell pillars adjacent thereto are arranged in a zigzag.

17. The semiconductor device of claim 16, wherein a distance between one of the dummy pillars and one of the cell pillars nearest to the one of the dummy pillars is less than a distance between a pair of immediately adjacent cell pillars.

18. The semiconductor device of claim 11, wherein the cell pillars are semiconductor pillars, and the semiconductor device further comprises:

a charge storage element between each of the semiconductor pillars and each of the horizontal electrodes.

19. The semiconductor device of claim 18, wherein the charge storage element comprises:

a charge storage layer;

a blocking insulating layer between the charge storage layer and each of the horizontal electrodes; and

a tunnel insulating layer between the charge storage layer and each of the semiconductor pillars.

20. The semiconductor device of claim 19, further comprising:

a common source line provided in the substrate overlapping with the first isolation insulating layer; and

a bit line coupled to the cell pillars.

21. The semiconductor device of claim 11, wherein the cell pillars are conductive pillars, and the semiconductor device further comprises:

a charge storage element between each of the conductive pillars and each of the horizontal electrodes,

wherein the charge storage element is a variable resistance pattern.

21-31. -31. (canceled)