FETS AND METHODS FOR FORMING THE SAME

• US 20150001468A1
• Filed: 09/12/2014
• Published: 01/01/2015
• Est. Priority Date: 02/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien, Fan, Chun-Hsiang, Lee, Tung Ying, Liu, Chi-Wen
• Granted Patent: US 9,362,386 B2
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/122 Single quantum well structures single heterojunctions, couples of materials H01L29/165, H01L29/205, H01L29/225, H01L29/267
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.

Claims

1. A structure comprising:

a substrate comprising a fin, the fin comprising an epitaxial channel region, the epitaxial channel having a major surface portion of an exterior surface, the major surface portion comprising at least one lattice shift, wherein the at least one lattice shift comprises an inward or outward shift relative to a center of the fin;

a gate dielectric on the major surface portion of the exterior surface; and

a gate electrode on the gate dielectric.

2. The structure of claim 1, wherein the epitaxial channel region comprises a quantum well along the exterior surface.

3. The structure of claim 1, wherein the gate dielectric substantially surrounds the epitaxial channel region.

4. The structure of claim 1, wherein the substrate has a substrate major surface, the major surface portion having a deviation angle from a normal to the substrate major surface exceeding 2 degrees.

5. The structure of claim 1, wherein the major surface portion has a defined crystalline surface orientation.

6. The structure of claim 1, wherein the major surface portion comprises a plurality of lattice shifts, the lattice shifts comprising a plurality of inward shifts.

7. A structure comprising:

a substrate having a major surface;

a transistor structure on the substrate and extending in a direction normal to the major surface, the transistor structure comprising a first source/drain region, a channel region, and a second source/drain region, the channel region being on the first source/drain region in the direction normal to the major surface, the second source/drain region being on the channel region in the direction normal to the major surface, the channel region having a sidewall surface, a deviation angle of the sidewall surface from the direction normal to the major surface exceeding 2 degrees; and

a gate structure surrounding the channel region in a plane perpendicular to the direction normal to the major surface.

8. The structure of claim 7, wherein the sidewall surface has a defined crystalline surface orientation.

9. The structure of claim 8, wherein the defined crystalline surface orientation is a (991) surface, a (881) surface, a (771) surface, a (661) surface, a (551) surface, a (441) surface, a (331) surface, or a (221) surface.

10. The structure of claim 7, wherein the channel region has a circular cross section in the plane perpendicular to the direction normal to the major surface.

11. The structure of claim 7, wherein the channel region has a rectangular cross section in the plane perpendicular to the direction normal to the major surface.

12. The structure of claim 7, wherein the sidewall surface comprises a lattice shift of at least two lattice spacings.

13. The structure of claim 7, wherein the sidewall surface comprises a plurality of lattice shifts, respective distances between neighboring lattice shifts being between 2 atoms and 20 atoms along a direction perpendicular to the lattice shifts.

14. A method comprising:

forming a channel region on a substrate;

after forming the channel region, re-shaping the channel region to have a major surface portion of a sidewall with a plurality of lattice shift locations, each of the plurality of lattice shift locations comprising an inward or outward lattice shift relative to a center of the channel region;

forming a dielectric on the major surface portion of the sidewall; and

forming a gate electrode on the dielectric.

15. The method of claim 14, wherein the re-shaping the channel region comprises a wet etch.

16. The method of claim 14, wherein the forming the channel region comprises:

forming a fin on the substrate; and

epitaxially growing a quantum well structure on the fin, the channel region comprising the quantum well structure.

17. The method of claim 14, wherein the forming the channel region comprises:

forming a fin on the substrate;

forming a recess in the fin; and

epitaxially growing the channel region in the recess in the fin.

18. The method of claim 17 further comprising after epitaxially growing the channel region, recessing the fin to form a void under the channel region, the forming the dielectric further comprising forming the dielectric in the void.

19. The method of claim 14, wherein the forming the channel region comprises:

epitaxially growing a channel layer on a first source/drain region;

epitaxially growing a second source/drain layer on the channel layer; and

patterning the second source/drain layer and the channel layer into a second source/drain region and the channel region, respectively.

20. The method of claim 14, wherein the re-shaping comprises a mixture of ammonium hydroxide and hydrochloric acid.