Methods for Coating a Substrate with an Amphiphilic Compound

• US 20150001555A1
• Filed: 09/17/2014
• Published: 01/01/2015
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: Intermolecular Incorporated (Merck & Co., Inc.)
• Original Assignee: Intermolecular Incorporated (Merck & Co., Inc.)
• Inventors: Duong, Anh, Chiang, Tony, Fresco, Zachary M., Kumar, Nitin, Lang, Chi-I, Tong, Jinhong, Tsizelmon, Anna
• Granted Patent: US 9,245,848 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: C09D 129/04 Polyvinyl alcohol; Partially hydrolysed homopolymers or copolymers of esters of unsaturated alcohols with saturated carboxylic acids
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31058 of organic layers
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

Claims

1. A semiconductor device comprising:

a substrate;

at least one dielectric region formed above the substrate, the at least one dielectric region having a surface on a side thereof opposite the substrate;

at least one conductive region formed above the substrate adjacent to the at least one dielectric region; and

an amphiphilic surface modifier layer formed on the surface of the at least one dielectric region to increase the hydrophilicity of the surface of the at least one dielectric region.

2. The semiconductor device of claim 1, wherein the amphiphilic surface modifier layer is a polyvinyl alcohol (PVA)-based surface modifier layer.

3. The semiconductor device of claim 2, wherein the at least one conductive region has a surface on a side thereof opposite the substrate, wherein the PVA-based surface modifier layer is not formed on the surface of the at least one conductive region.

4. The semiconductor device of claim 2, wherein the PVA-based surface modifier layer comprises a co-polymer selected from the group consisting of co-ethylene, co-cation, co-siloxane, co-anion (88% hydrolyzed), and co-anion (80% hydrolyzed).

5. The semiconductor device of claim 2, wherein the PVA-based surface modifier layer has a thickness of between 5 and 50 Angstroms (Å

).

6. The semiconductor device of claim 5, wherein the PVA-based surface modifier layer has a thickness of between 20 and 35 Å

.

7. The semiconductor device of claim 2, wherein the at least one dielectric region comprises a low-k dielectric material.

8. The semiconductor device of claim 7, wherein the low-k dielectric material comprises at least one of SiO₂, SiCN, SiCNH, SiCH₃, SiOCH₃, SiCOH, porous SiCOH, SiN, SiC, methyl-silsesquioxane (MSQ), SiLK dielectric, parylene, organic low-k polymers, or a combination thereof.

9. The semiconductor device of claim 7, wherein the at least one conductive region comprises at least one of copper, aluminum, a copper-zinc alloy, a copper-calcium alloy, a copper-manganese alloy, or a combination thereof.

10. The semiconductor device of claim 7, wherein the substrate comprises one of a silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a strained silicon substrate, a silicon germanium substrate, or a gallium arsenide substrate.

15. The semiconductor device of claim 4, wherein each of the plurality of conductive regions has a surface on a side thereof opposite the substrate, wherein the PVA-based surface modifier layer is not formed on the surface of each of the plurality of conductive regions.

16. The semiconductor device of claim 15, wherein each of the plurality of low-k dielectric regions comprises at least one of SiO₂, SiCN, SiCNH, SiCH₃, SiOCH₃, SiCOH, porous SiCOH, SiN, SiC, methyl-silsesquioxane (MSQ), SiLK dielectric, parylene, organic low-k polymers, or a combination thereof.

17. The semiconductor device of claim 16, wherein each of the plurality of conductive regions comprises at least one of copper, aluminum, a copper-zinc alloy, a copper-calcium alloy, a copper-manganese alloy, or a combination thereof.

18. The semiconductor device of claim 17, wherein the substrate comprises at least one of a silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a strained silicon substrate, a silicon germanium substrate, or a gallium arsenide substrate.

11. A semiconductor device comprising:

a substrate;

a plurality of low-k dielectric regions formed above the substrate, each of the plurality of low-k dielectric regions having a surface on a side thereof opposite the substrate;

a plurality of conductive regions formed above the substrate, each of the plurality of conductive regions being between and adjacent to two of the plurality of low-k dielectric regions; and

a polyvinyl alcohol (PVA)-based surface modifier layer formed on the surface of each of the plurality of low-k dielectric regions to increase the hydrophilicity of the surface of each of the plurality of low-k dielectric regions.

12. The semiconductor device of claim 11, wherein the PVA-based surface modifier layer comprises a co-polymer selected from the group consisting of co-ethylene, co-cation, co-siloxane, co-anion (88% hydrolyzed), and co-anion (80% hydrolyzed).

13. The semiconductor device of claim 12, wherein the PVA-based surface modifier layer has a thickness of between 5 and 50 Angstroms (Å

).

14. The semiconductor device of claim 13, wherein the PVA-based surface modifier layer has a thickness of between 20 and 35 Å

.