MULTICHIP MODULE WITH STIFFING FRAME AND ASSOCIATED COVERS

• US 20150001701A1
• Filed: 06/27/2013
• Published: 01/01/2015
• Est. Priority Date: 06/27/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Monjeau, Gregg B., Sikka, Kamal K., Toy, Hilton T., Weiss, Thomas, Li, Shidong
• Granted Patent: US 9,089,051 B2
• Time in Patent Office: Days
• US Class Current: 257/713
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/02 Containers; Seals H01L23/12, H01L23/34, H01L23/48, H01L23/552, H01L23/66 take precedence; for memories G11C
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/433 Auxiliary members in containers characterised by their shape, e.g. pistons
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0204 using means for thermal conduction connection in the thickness direction of the substrate H05K1/0207 takes precedence
• CPC Class Codes: H05K 5/03 Covers

Abstract

A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings.

Claims

1. A method comprising:

attaching a stiffening frame to a carrier with a compliant adhesive that absorbs thermally induced dimensional variations between the stiffening frame and the carrier, the stiffening frame comprising a plurality of openings configured to accept a plurality of semiconductor chips;

electronically coupling the plurality of semiconductor chips to the carrier, each semiconductor chip being concentrically arranged within a particular opening, and;

attaching a plurality of covers to the stiffening frame to enclose the plurality of openings.

2. The method of claim 1 wherein at least a first cover is in thermal contact with a first semiconductor chip.

3. The method of claim 1 further comprising:

attaching a thermal interface material barrier to the stiffening frame perimeter.

4. The method of claim 1 wherein each cover comprises a top surface and wherein the top surface of a first cover is coplanar with the top surface of a second cover.

5. The method of claim 1 wherein each cover comprises a top surface and wherein the top surface of a first cover is non-planar with the top surface of a second cover.

6. The method of claim 1 wherein each cover comprises a top surface, wherein the stiffening frame comprises a top surface, and wherein the top surface of a first cover is coplanar with the top surface of the stiffening frame.

7. The method of claim 1 wherein the plurality of semiconductor chips are arranged in a homogenous chipset.

8. The method of claim 1 wherein the plurality of semiconductor chips are arranged in a heterogeneous chipset.

9-16. -16. (canceled)

17. A method comprising:

electrically connecting a multichip module to a motherboard, the multichip module comprising;

a carrier comprising;

a top surface and a bottom surface configured to be electrically connected to a motherboard;

a stiffening frame attached to the top surface with an compliant adhesive that absorbs thermally induced dimensional variations between the stiffening frame and the carrier, the stiffening frame comprising;

a plurality of openings that accept the plurality of semiconductor chips;

a plurality of semiconductor chips electrically connected to the top surface and concentrically arranged within the plurality of openings, and;

a plurality of covers attached to the stiffening frame that enclose the plurality of openings;

thermally attaching a heat sink to the multichip module with a thermal interface material juxtaposed there between, the thermal interface material being dimensionally compliant to absorb dimensional differences between the plurality of covers and the heat sink.

18. The method of claim 17 wherein each cover comprises a top surface and wherein the top surface of a first cover is non-planar with the top surface of a second cover.

19. The method of claim 17 wherein at least a first cover is in thermal contact with a first semiconductor chip.

20. The method of claim 17 wherein the stiffening frame further comprises a thermal interface material barrier upon a top surface of the stiffening frame perimeter and

wherein the thermal interface material is applied in the area within the thermal interface material barrier.