Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package

• US 20150001708A1
• Filed: 06/28/2013
• Published: 01/01/2015
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian
• Granted Patent: US 8,980,691 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1082 for improving alignment between containers, e.g. interlocking features
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device includes a substrate having an insulating layer and a conductive layer embedded in the insulating layer. The conductive layer is patterned to form conductive pads or conductive pillars. The substrate includes a first encapsulant formed over the conductive layer. A first opening is formed through insulating layer and first encapsulant using a stamping process or laser direct ablation. The substrate is separated into individual units, which are mounted to a carrier. A semiconductor die is disposed in the first opening in the substrate. A second encapsulant is deposited over the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and substrate. An opening is formed through the second encapsulant and through the insulating layer to expose the conductive layer. A bump is formed in the second opening over the conductive layer outside a footprint of the semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a substrate including a first insulating layer and a conductive layer embedded in the first insulating layer and a first opening extending completely through the substrate;

disposing a first semiconductor die within the first opening of the substrate;

depositing an encapsulant over the first semiconductor die and substrate; and

forming a second opening through the encapsulant and substrate extending to the conductive layer.

2. The method of claim 1, further including forming an interconnect structure over the first semiconductor die and substrate.

3. The method of claim 1, further including forming a bump within the second opening over the conductive layer.

4. The method of claim 1, further including removing a portion of the first semiconductor die and encapsulant.

5. The method of claim 1, wherein providing the substrate further includes:

forming a bump over the conductive layer; and

forming the first insulating layer over the conductive layer and the bump.

6. The method of claim 1, further including disposing a second semiconductor die over the first semiconductor die.

29. The method of claim 1, further including forming the first opening or second opening by stamping or laser direct ablation.

30. The method of claim 1, further including forming a second insulating layer over the first insulating layer.

7. A method of making a semiconductor device, comprising:

providing a substrate including a first insulating layer and a conductive layer;

forming a first opening through the substrate;

disposing a first semiconductor die within the first opening of the substrate; and

forming a second opening partially through the substrate extending to the conductive layer.

8. The method of claim 7, further including forming an interconnect structure over the first semiconductor die and substrate.

10. The method of claim 7, further including:

depositing an encapsulant over the first semiconductor die and substrate; and

forming the second opening through the encapsulant and substrate extending to the conductive layer.

11. The method of claim 7, further including forming a bump within the second opening over the conductive layer.

12. The method of claim 7, further including forming the first opening or second opening by stamping or laser direct ablation.

31. The method of claim 7, further including forming a second insulating layer over the first insulating layer.

32. The method of claim 7, further including disposing a second semiconductor die over the first semiconductor die.

9. (canceled)

13. (canceled)

14. A semiconductor device, comprising:

a substrate including a first opening extending through the substrate;

a first semiconductor die disposed in the first opening of the substrate;

an encapsulant deposited over the first semiconductor die and substrate; and

a second opening formed through the encapsulant and partially through the substrate.

15. The semiconductor device of claim 14, wherein the substrate further includes:

an insulating layer; and

a conductive layer embedded within the insulating layer.

16. The semiconductor device of claim 15, wherein the conductive layer includes conductive pads or pillars having a pitch of 0.50 millimeters or less.

19. The semiconductor device of claim 14, further including an interconnect structure formed over the first semiconductor die and substrate.

20. The semiconductor device of claim 14, further including a bump formed in the second opening.

33. The semiconductor device of claim 14, further including a second semiconductor die disposed over the first semiconductor die.

17-18. -18. (canceled)

21. A semiconductor device, comprising:

a substrate including a first insulating layer and a conductive layer, wherein a first surface of the conductive layer and a second surface of the conductive layer opposite the first surface are devoid of the first insulating layer and a height of the conductive layer is less than a height of the first insulating layer; and

a first semiconductor die disposed adjacent to the substrate.

22. The semiconductor device of claim 21, further including an interconnect structure formed over the first semiconductor die and substrate.

23. The semiconductor device of claim 21, further including a bump formed in the second opening over the conductive layer.

24. The semiconductor device of claim 21, further including an encapsulant deposited over the first semiconductor die and substrate.

25. The semiconductor device of claim 21, further including a second semiconductor die disposed over the first semiconductor die.

26. The semiconductor device of claim 24, wherein the second opening extends through the encapsulant and partially through the substrate.

27. The semiconductor device of claim 21, further including a heat sink disposed over the first semiconductor die.

28. The semiconductor device of claim 21, further including a second insulating layer formed over the first insulating layer.

34. A method of making a semiconductor device, comprising:

providing a plurality of substrate units each including an insulating layer and a conductive layer embedded in the insulating layer;

arranging the substrate units to form a space between the substrate units;

disposing a first semiconductor die in the space between the substrate units; and

forming an opening in the substrate units extending to the conductive layer.

35. The method of claim 34, further including forming an interconnect structure over the first semiconductor die and substrate units.

36. The method of claim 34, further including depositing an encapsulant over the first semiconductor die and substrate units.

37. The method of claim 36, further including forming the opening through the encapsulant and substrate units extending to the conductive layer.

38. The method of claim 34, further including forming a bump within the opening over the conductive layer.

39. The method of claim 34, further including disposing a second semiconductor die over the first semiconductor die.