Semiconductor Devices Employing a Barrier Layer

• US 20150001723A1
• Filed: 09/18/2014
• Published: 01/01/2015
• Est. Priority Date: 01/04/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chien, Ying-Hsueh Chang, Lee, Yu-Ming, Leung, Man-Kit, Yang, Chi-Ming
• Granted Patent: US 10,510,655 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53233 Copper alloys
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 80/30 Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

A semiconductor device includes providing a workpiece including an insulating material layer disposed thereon. The insulating material layer includes a trench formed therein. A barrier layer on the sidewalls of the trench is formed using a surface modification process and a surface treatment process.

Claims

1. A semiconductor device, comprising:

a workpiece;

a conductive feature formed over the workpiece;

an insulating material layer disposed over the conductive feature;

a via coupled to the conductive feature, the via being disposed in the insulating material; and

a barrier layer disposed on sidewalls of the via proximate the insulating material layer, wherein the barrier layer comprises a material selected from the group consisting of hydrocarbon, halocarbon, sulfured carbon, silicon carbon, graphite, graphene, amorphous carbon, fullerene, and combinations thereof.

2. The semiconductor device according to claim 1, wherein the insulating material layer comprises a low dielectric constant (k) insulating material having a dielectric constant of about 3.9 or less.

3. The semiconductor device according to claim 1, wherein the conductive feature comprises Cu or a Cu alloy.

4. The semiconductor device according to claim 1, wherein the via comprises Cu or a Cu alloy.

5. The semiconductor device according to claim 1, further comprising a seed layer formed on the barrier layer.

6. The semiconductor device according to claim 1, further comprising an etch stop layer interjacent the conductive feature and the insulating layer.

7. The semiconductor device according to claim 6, further comprising a second etch stop layer overlying the insulating layer.

8. The semiconductor device according to claim 1, wherein the barrier layer comprises a portion of the insulating layer combined with a material selected from the group consisting of hydrocarbon, halocarbon, sulfured carbon, silicon carbon, graphite, graphene, amorphous carbon, fullerene, and combinations thereof.

9. The semiconductor device according to claim 1, wherein the barrier layer comprises a damaged portion of the insulating layer combined with a material selected from the group consisting of hydrocarbon, halocarbon, sulfured carbon, silicon carbon, graphite, graphene, amorphous carbon, fullerene, and combinations thereof.

10. The semiconductor according to claim 1, wherein the barrier layer further comprises a material selected from the group consisting of cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, and/or combinations thereof.

11. A semiconductor device comprising:

an interconnect line formed over a substrate;

an etch stop layer formed over at least part of the interconnect line;

an insulating material formed over the etch stop layer and having a trench therein, the trench including sidewalls, the insulating material including a bulk region and a converted region, the converted region lining the sidewalls of the trench and comprising a material selected from the group consisting essentially of a material selected from the group consisting of hydrocarbon, halocarbon, sulfured carbon, silicon carbon, graphite, graphene, amorphous carbon, fullerene, and combinations thereof; and

a conductive via formed within the trench and in electrical contact with the interconnect line.

12. The semiconductor device according to claim 11, wherein the converted region further comprises a material selected from the group consisting of cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, and/or combinations thereof.

13. The semiconductor device according to claim 11, wherein the insulating material comprises a low dielectric constant material with a dielectric constant below 3.9.

14. The semiconductor device according to claim 11, wherein the insulating material comprises boron-doped silicon glass (BSG), phosphosilicate glass (PSG), fluorinated silicate glass (FSG), SiCOH, and combinations thereof.

15. The semiconductor device according to claim 11, wherein the converted region acts as a barrier layer.

16. A semiconductor device comprising:

a patterned dielectric layer having an opening therein that exposes an underlying conductive feature;

a barrier layer lining sidewalls of the opening, the barrier layer including a first component comprising a material selected from the group consisting of cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, and/or combinations thereof, and a second component comprising a material selected from the group consisting of hydrocarbon, halocarbon, sulfured carbon, silicon carbon, graphite, graphene, amorphous carbon, fullerene, and combinations thereof; and

a conductive plug in the opening.

17. The semiconductor device according to claim 16, wherein the patterned dielectric layer is a material selected from the group consisting of boron-doped silicon glass (BSG), phosphosilicate glass (PSG), fluorinated silicate glass (FSG), SiCOH, and combinations thereof.

18. The semiconductor device according to claim 16, wherein the conductive feature is a material selected from the group consisting of copper and copper alloys.

19. The semiconductor device according to claim 16, wherein the patterned dielectric layer has a dielectric constant value of less than about 2.5.

20. The semiconductor device according to claim 16, wherein the barrier layer has a hydrophobic surface.