SYSTEM AND METHOD FOR VARIABLE FREQUENCY CLOCK GENERATION
First Claim
1. A clock generation circuit, comprising:
- a detection circuit configured to detect a change in a voltage supply signal coupled to the clock generation circuit; and
a control circuit coupled to the detection circuit and configured to alter a control signal for regulating a current-controlled oscillator in response to detecting the change.
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0 Petitions
Accused Products
Abstract
A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.
36 Citations
31 Claims
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1. A clock generation circuit, comprising:
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a detection circuit configured to detect a change in a voltage supply signal coupled to the clock generation circuit; and a control circuit coupled to the detection circuit and configured to alter a control signal for regulating a current-controlled oscillator in response to detecting the change. - View Dependent Claims (2, 3, 5, 6, 7, 8, 9, 10)
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4. (canceled)
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11. A method, comprising:
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monitoring a supply voltage; generating a digital control word for generating the clock signal; and in response to detecting the supply voltage falling below a threshold, causing a clock signal to be reduced by ramping the digital control word toward generating a clock signal with a lower frequency. - View Dependent Claims (12, 14, 15, 16, 17, 18, 19, 20, 21)
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13. (canceled)
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22. A method, comprising:
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generating a clock signal in a frequency locked loop, the frequency of the clock signal controlled by a control signal; in response to detecting a supply voltage falling below a threshold voltage; subtracting current from the control signal. - View Dependent Claims (23, 24)
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25. A system, comprising:
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a voltage supply node a first electronic component having a clock generator circuit and coupled to the voltage supply node, including; a detection circuit configured to detect a change in voltage at the voltage supply node; and a control circuit coupled to the detection circuit and configured to alter a control signal for regulating a current-controlled oscillator in response to detecting the change; and a second electronic component coupled to the first electronic component. - View Dependent Claims (26, 27, 28)
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29. An integrated circuit, comprising:
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a voltage supply node; a detection circuit configured to detect a change in voltage at the voltage supply node; and a control circuit coupled to the detection circuit and configured to subtract current from a control signal for regulating a system clock in response to detecting the change.
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30. An integrated circuit, comprising:
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a voltage supply node a detection circuit configured to detect a change in voltage at the voltage supply node; and a control circuit coupled to the detection circuit and configured to engage a current sink that sinks half of a current of a control signal for regulating a system clock in response to detecting the change.
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31. An integrated circuit, comprising:
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a voltage supply node a detection circuit configured to detect a change in voltage at the voltage supply node; and a control circuit coupled to the detection circuit and configured to immediately ramp a system clock signal in response to detecting the change.
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Specification