FINFET-BASED BOOSTING SUPPLY VOLTAGE CIRCUIT AND METHOD

• US 20150003174A1
• Filed: 07/26/2013
• Published: 01/01/2015
• Est. Priority Date: 07/01/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Joshi, Rajiv V., Kim, Keunwoo
• Granted Patent: US 9,036,430 B2
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first transistor is a planar transistor, a source of the first transistor being connected with the voltage supply, and a gate of the first transistor receiving a control signal. The second transistor includes a gate formed in at least two planes. A source of the second transistor is connected with the voltage supply, a gate of the second transistor receives the control signal, and a drain of the second transistor is connected with a drain of the first transistor and forms an output of the voltage boosting circuit for generating a boosted supply voltage as a function of the control signal.

Claims

1. A method for generating an output voltage supplied to a circuit, the output voltage having a magnitude that is greater than a voltage generated by a voltage supply of the circuit, the method comprising:

providing a first transistor, the first transistor being a planar transistor;

connecting a first source/drain of the first transistor with the voltage supply of the circuit;

providing a second transistor having a gate formed in at least two planes;

connecting a first source/drain of the second transistor with the voltage supply;

supplying a control signal to a gate of each of the first and second transistors;

connecting a second source/drain of the second transistor with a second source/drain of the first transistor to form an output for generating a boosted supply voltage as a function of the control signal.

2. The method of claim 1, further comprising connecting the output with at least one of a plurality of memory cells and logic circuitry in a memory circuit for reducing a minimum operating voltage of the memory circuit.

3. The method of claim 1, further comprising configuring a level of the voltage supply of the circuit such that a period of time during which the boosted supply voltage exceeds the level of the voltage supply of the circuit is substantially equal to a period of time between subsequent changes of state of the control signal.

4. The method of claim 1, wherein the second transistor comprises at least one of a fin-shaped field-effect transistor (FinFET), a nanowire transistor, and a T-shaped field-effect transistor (T-FET).

5. The method of claim 1, further comprising connecting the boosted supply voltage with at least one of a plurality of memory cells and logic circuitry in a memory circuit for reducing a minimum operating voltage of the memory circuit.

6. The method of claim 1, wherein when the control signal transitions from a first logic level, at which the second transistor is inactive, to a second logic level, at which the second transistor is active, capacitive coupling in the second transistor is operative to pull the boosted supply voltage up to a level that exceeds a level of the voltage supply of the voltage boosting circuit for a period of time equal to at least a portion of an interval during which the control signal is at the second logic level.

7. The method of claim 6, further comprising configuring the level of the voltage supply of the voltage boosting circuit such that the period of time during which the boosted supply voltage exceeds the level of the voltage supply of the voltage boosting circuit is substantially equal to a period of time between subsequent changes of state of the control signal supplied to the voltage boosting circuit.

8. The method of claim 1, further comprising configuring the voltage boosting circuit such that an amplitude of the boosted supply voltage is a function of a slew rate of the control signal supplied to the voltage boosting circuit.

9. The method of claim 1, further comprising connecting the output of the voltage boosting circuit with a voltage supply node of at least one word line driver circuit, the at least one word line driver circuit generating a boosted word line signal as a function of the control signal supplied to the voltage boosting circuit.