Baseband Cancellation of Direct Sequence Spread Spectrum Platform Radio Interference

• US 20150003500A1
• Filed: 06/27/2013
• Published: 01/01/2015
• Est. Priority Date: 06/27/2013
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Dawson W. Kesling
• Inventors: Kesling, Dawson W.
• Application Number:
  US13/928,468
• Publication Number:
  US 20150003500A1
• Time in Patent Office: Days
• US Class Current: 375/148
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04B 1/7097 Interference-related aspects

Abstract

Briefly, in accordance with one or more embodiments, a platform may comprise a receiver to receive a signal that includes an error in the received signal due to a noise signal generated in the platform, and a processor configured to calculate a noise vector from a source of the noise signal. The noise vector may be de-spread. The receiver may include digital signal processing configured to estimate an error vector based at least in part on the noise vector and to subtract the estimated error vector from the received signal to cancel the noise signal from the received signal. The noise cancelled from the received signal may include platform noise generated by a bus, a memory circuit, a clock, a power supply, a circuit ground or integrated circuit substrate, or input/output circuit of the platform.

Claims

1. A platform comprising:

a direct sequence spread spectrum receiver to receive a signal including a platform generated noise signal;

a device to calculate a noise vector at a chip rate;

a de-spreader to de-spread the noise vector;

an adaptive filter to receive the de-spread noise vector and use the de-spread noise vector to determine an error vector at the chip rate; and

a subtractor to subtract the error vector from the received signal at the chip rate.

2. A platform as claimed in claim 1, wherein the noise signal is generated from a bus, a memory circuit, a clock, a power supply, a circuit ground or integrated circuit substrate, or an input/output circuit of the platform.

3. A platform as claimed in claim 1, wherein the device is further configured to synchronize the calculated noise vectors with a symbol time of the receiver.

4. A platform as claimed in claim 1, wherein the device is further configured to implement two or more noise vector generation and processing blocks to arrive at a combined estimated error vector for two or more noise signals from two or more sources or paths.

5. A platform of claim 1 including a front end coupled to the subtractor, coupled to a de-spread, coupled to a constellation de-mapper.

6. A platform of claim 5 including an output of said de-mapper to feed error vectors to said filter.

7. A platform of claim 6, said filter to receive noise vectors and de-spread noise vectors.

10. A platform of claim 1 including a multiplier and said noise vector being input to said multiplier, both with and without de-spreading.

11. A platform of claim 1 including a touch screen display, keyboard, memory port, multiple antennas, a graphics processor, and speakers.

8-9. -9. (canceled)

12. A method comprising:

calculating noise vector based on bus noise;

de-spreading the noise vector;

receiving the de-spread noise vector;

using the de-spread noise vector to determine an error vector at the chip rate; and

subtracting the error vector from the received signal at the chip rate.

13. A method as claimed in claim 12 including receiving a noise signal generated from a bus, a memory circuit, a clock, a power supply, a circuit ground or integrated circuit substrate, or an input/output circuit of a platform.

14. A method as claimed in claim 12 including synchronizing the calculated noise vectors with a symbol time of a receiver.

15. A method as claimed in claim 12 including implementing two or more noise vector generation and processing blocks to arrive at a combined estimated error vector for two or more noise signals from two or more sources or paths.

16. A method of claim 12 including calculating noise vectors at a spreading or chip rate and de-spreading to a symbol rate.

17. A method of claim 12 including multiplying noise vector both with and without de-spreading.

18. One or more non-transitory computer readable media storing instructions to perform a sequence comprising:

receiving a direct spread spectrum signal including noise generated by a bus device;

calculating a noise vector based on said noise;

de-spreading the noise vector;

using the de-spread noise vector to determine an error vector at the chip rate; and

subtracting the error vector from the received signal at the chip rate.

19. The media of claim 18 further storing instructions to perform a sequence including receiving a noise signal generated from a bus, a memory circuit, a clock, a power supply, a circuit ground or integrated circuit substrate, or an input/output circuit of a platform.

20. The media of claim 18 further storing instructions to perform a sequence including synchronizing the calculated noise vectors with a symbol time of a receiver.

21. The media of claim 18 further storing instructions to perform a sequence including implementing two or more noise vector generation and processing blocks to arrive at a combined estimated error vector for two or more noise signals from two or more sources or paths.

22. The media of claim 18 further storing instructions to perform a sequence including calculating noise vectors at a spread or chip rate and de-spreading to a symbol rate.

23. The media of claim 18 further storing instructions to perform a sequence including multiplying noise vector both with and without de-spreading.

24. The media of claim 18 further storing instructions to perform a sequence including providing an output of de-mapper to feed error vectors for said filtering.

25. The media of claim 18 further storing instructions to perform a sequence including providing noise vectors without de-spreading and with de-spreading to said filtering.