OUTPUT SIGNAL GENERATING METHOD, DECODED DATA GENERATING METHOD, OUTPUT SIGNAL GENERATING APPARATUS, AND DECODED DATA GENERATING APPARATUS

• US 20150003564A1
• Filed: 09/16/2014
• Published: 01/01/2015
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Inventors: MURAKAMI, Yutaka, Okamura, Shutai, Kobayashi, Kiyotaka, Takahashi, Kazuaki, Orihashi, Masayuki
• Granted Patent: US 9,712,280 B2
• Time in Patent Office: Days
• US Class Current: 375/298
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/22 using redundant apparatus to increase reliability
• CPC Class Codes: H04L 27/0008 arrangements for allowing a transmitter or receiver to use more than one type of modulation negotiating modulation type for two-way transmission paths H04L5/1453
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04L 27/36 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 5/0007 the frequencies being orthogonal, e.g. OFDM(A), DMT

Abstract

A transmitter apparatus wherein a simple structure is used to successfully suppress the degradation of error rate performance that otherwise would be caused by fading or the like. There are included encoding parts that encode transport data; a mapping part that performs such a mapping that encoded data sequentially formed by the encoding parts are not successively included in the same symbol, thereby forming data symbols; and a symbol interleaver that interleaves the data symbols. In this way, a low computational complexity can be used to perform an interleaving process equivalent to a bit interleaving process to effectively improve the reception quality at a receiving end.

Claims

1. An output signal generating method comprising:

generating, by a processor, a plurality of encoded data sequences configured by a predetermined number of bits, by encoding transmit data configured by a plurality of bits;

generating one symbol sequence by one modulating process, selected from a plurality of modulating processes, on the encoded data sequences; and

outputting one baseband signal sequence generated by using an OFDM scheme, for the one symbol sequence, wherein;

the one modulating process generates the one symbol sequence configured by QPSK symbols generated by using a QPSK scheme or 16QAM symbols generated by using a 16QAM scheme;

the one symbol sequence generated by using the QPSK scheme is configured with first two encoded data sequences in the plurality of encoded data sequences;

the one symbol sequence generated by using the 16QAM scheme is configured with the first two encoded data sequences and second two encoded data sequences in the plurality of encoded data sequences;

a number of the 16QAM symbols is the same as a number of the QPSK symbols in the one symbol sequence;

specific two bits extracted from a plurality of bits configuring the QPSK symbols and the 16QAM symbols in the one symbol sequence are bits belonging to the first two encoded data sequences;

a number of the encoded data sequences is changed according to the selected one modulating process; and

each of the encoded data sequences is configured with LDPC encoded data.

2. The output signal generating method according to claim 1, wherein other two bits different from the specific two bits in the plurality of bits configuring the 16QAM symbols are bits belonging to the second encoded data sequence different from the first encoded data sequence.

3. A decoded data generating method comprising:

inputting one modulated signal sequence generated by using an OFDM scheme;

generating, by a processor, one symbol sequence from the one modulated signal sequence;

generating a plurality of encoded data sequences configured by a predetermined number of bits, from the one symbol sequence; and

generating decoded data configured by a plurality of bits, by decoding the plurality of encoded data sequences, wherein;

the one symbol sequence includes either QPSK symbols generated by using a QPSK scheme or 16QAM symbols generated by using a 16QAM scheme;

the one symbol sequence generated by using the QPSK scheme is configured with first two encoded data sequences in the plurality of encoded data sequences;

the one symbol sequence generated by using the 16QAM scheme is configured with the first two encoded data sequences and second two encoded data sequences in the plurality of encoded data sequences;

a number of the 16QAM symbols is the same as a number of the QPSK symbols in the one symbol sequence;

specific two bits extracted from a plurality of bits configuring the QPSK symbols and the 16QAM symbols in the one symbol sequence are bits belonging to the first two encoded data sequence;

a number of the encoded data sequences is changed according to the selected one modulating process; and

each of the encoded data sequences is configured with LDPC encoded data.

4. The decoded data generating method according to claim 3, wherein other two bits different from the specific two bits in the plurality of bits configuring the 16QAM symbols are bits belonging to the second encoded data sequence different from the first encoded data sequence.

5. An output signal generating apparatus comprising:

an encoding section structured to generate a plurality of encoded data sequences configured by a predetermined number of bits, by encoding transmit data configured by a plurality of bits; and

a modulation section structured to select one modulating process from a plurality of modulating processes, to generate one symbol sequence by the selected one modulating process on the encoded data sequences, and to output one baseband signal sequence generating by using an OFDM scheme for the one symbol sequence, wherein;

the one modulating process generates the one symbol sequence configured by QPSK symbols generated by using a QPSK scheme or 16QAM symbols generated by using a 16QAM scheme;

the one symbol sequence generated by using the QPSK scheme is configured with first two encoded data sequences in the plurality of encoded data sequences;

the one symbol sequence generated by using the 16QAM scheme is configured with the first two encoded data sequences and second two encoded data sequences in the plurality of encoded data sequences;

a number of the 16QAM symbols is the same as a number of the QPSK symbols in the one symbol sequence;

specific two bits extracted from a plurality of bits configuring the QPSK symbols and the 16QAM symbols in the one symbol sequence are bits belonging to the first two encoded data sequences;

a number of the encoded data sequences is changed according to the selected one modulating process; and

each of the encoded data sequences is configured with LDPC encoded data.

6. The output signal generating apparatus according to claim 5, wherein other two bits different from the specific two bits in the plurality of bits configuring the 16QAM symbols are bits belonging to the second encoded data sequence different from the first encoded data sequence.

7. A decoded data generating apparatus comprising:

an input section structured to input one modulated signal sequence generated by using an OFDM scheme;

a demodulation section structured to generate one symbol sequence from the one modulated signal sequence, and to generate a plurality of encoded data sequences configured by a predetermined number of bits, from the one symbol sequence; and

a decoding section structured to generate decoded data configured by a plurality of bits, by decoding the plurality of encoded data sequences, wherein;

the one symbol sequence includes either QPSK symbols generated by using a QPSK scheme or 16QAM symbols generated by using a 16QAM scheme;

the one symbol sequence generated by using the QPSK scheme is configured with first two encoded data sequences in the plurality of encoded data sequences;

the one symbol sequence generated by using the 16QAM scheme is configured with the first two encoded data sequences and second two encoded data sequences in the plurality of encoded data sequences;

a number of the 16QAM symbols is the same as a number of the QPSK symbols in the one symbol sequence;

specific two bits extracted from a plurality of bits configuring the QPSK symbols and the 16 QAM symbols in the one symbol sequence are bits belonging to the first two encoded data sequence;

a number of the encoded data sequences is changed according to the selected one modulating process; and

each of the encoded data sequences is configured with LDPC encoded data.

8. The output signal generating apparatus according to claim 7, wherein other two bits different from the specific two bits in the plurality of bits configuring the 16QAM symbols are bits belonging to the second encoded data sequence different from the first encoded data sequence.