ENCAPSULATED ELECTRONIC CIRCUIT

• US 20150005573A1
• Filed: 07/01/2014
• Published: 01/01/2015
• Est. Priority Date: 07/01/2013
• Status: Active Grant

• Current Assignee: NewSouth Innovations Pty Limited (University Of New South Wales)
• Original Assignee: NewSouth Innovations Pty Limited (University Of New South Wales)
• Inventors: LEHMANN, Torsten, SUANING, Gregg Jrgen, NYGARD, Tony Mikael, GUENTHER, Thomas, LIM, William, DAS, Kushal
• Granted Patent: US 9,884,197 B2
• Time in Patent Office: Days
• US Class Current: 600/25
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/36038 Cochlear stimulation
• CPC Class Codes: A61N 1/375 Constructional arrangements, e.g. casings
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04R 2460/13 Hearing devices using bone conduction transducers
• CPC Class Codes: H04R 25/606 acting directly on the eardrum, the ossicles or the skull, e.g. mastoid, tooth, maxillary or mandibular bone, or mechanically stimulating the cochlea, e.g. at the oval window
• CPC Class Codes: H05K 3/284 for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths

Abstract

A device, including an implantable electronic circuit integrated at least one of in or on a substrate, wherein the device includes a hermetic enclosure having a space therein, wherein the substrate forms at least a portion of the hermetic enclosure.

Claims

1. A device, comprising:

an implantable electronic circuit integrated at least one of in or on a substrate, wherein the device includes a hermetic enclosure having a space therein, wherein the substrate forms at least a portion of the hermetic enclosure.

2. The device of claim 1, wherein:

the device includes a housing configured to hermetically isolate the space and the electronic circuit from an environment in a body of a recipient; and

the substrate forms a wall of the housing.

3. The device of claim 2, wherein:

a height of the housing as measured normal to a span-wise direction of the substrate and through the space is no more than about five times a thickness of the substrate, also measured normal to the span-wise direction.

4. The device of claim 2, wherein:

a height of the housing as measured normal to a span-wise direction of the substrate and through the space is no more than about three times a thickness of the substrate, also measured normal to the span-wise direction.

5. The device of claim 2, wherein:

the space is an air-gap between a surface of the substrate and a surface of an adjacent wall of the housing opposite the surface of the substrate, and wherein a height of the housing as measured normal to a span-wise direction of the substrate and through the air-gap is no more than about 1,000 microns.

6. The device of claim 2, wherein:

the space is an air-gap between a surface of the substrate and a surface of an adjacent wall of the housing opposite the surface of the substrate, and wherein a height of the housing as measured normal to a span-wise direction of the substrate and through the air-gap is no more than about 500 microns.

7. The device of claim 1, further comprising:

an encapsulation component, at least a portion of which is spaced away from the substrate, wherein the substrate and the encapsulation component form at least a portion of the hermetic enclosure, and wherein the space in the hermetic enclosure is established at least in part by the spacing away of the encapsulation component from the substrate.

8. The device of claim 1, wherein the encapsulation component is a shell being of the same type of material as the substrate.

9. The device of claim 1, wherein the electronic circuit is an integrated silicone-on sapphire circuit.

10. A device, comprising:

an implantable housing configured to establish a hermetic volume therein, wherein the device is configured to enable hermeticity testing via active sensing of one or more phenomena in the hermetic volume.

11. The device of claim 10, further comprising:

a hermeticity sensor component at least one of internal or integral to the housing, wherein the hermeticity sensor component is configured to enable active sensation of the one or more phenomena, thereby enabling the hermeticity testing.

12. The device of claim 11, wherein:

a wall of the housing includes an electronic circuit integrated therein that includes a hermeticity sensor, and at least a part of the hermeticity sensor component being an integrated part of the electronic circuit and part of the hermeticity sensor.

13. The device of claim 11, wherein:

the hermeticity sensor component enables the evaluation of a physical phenomenon associated with at least one of an electrical capacitance or an electrical resistance of a structure exposed to the volume, and enables an output of a signal indicative of a change in the physical phenomenon, thereby indicating a change in a status of hermeticicy of the volume.

14. The device of claim 13, wherein:

the device includes a substrate at least one of in which or on which is located an interdigitized exposed pattern corresponding to the structure exposed to the volume.

15. The device of claim 10, further comprising:

a palladium wire exposed to the hermetic volume, wherein the palladium wire is in electrical communication with a location on the housing exposed to an ambient environment of the housing.

16. The device of claim 15, wherein the device includes one or more electrical interfaces integral with the housing, the one or more electrical interfaces corresponding to the location on the housing exposed to an ambient environment.

17. The device of claim 10, wherein:

the device is configured to actively sense helium intrusion into an almost-hermetic volume of about 20 mm³ or less.

18. A method, comprising:

obtaining a substrate having vias extending therethrough from a first face to a second face opposite the first face;

applying a first electrically conductive material onto a first face of the substrate over the vias; and

inserting a second electrically conductive material into the vias, such that the second electrically conductive material extends to the second face of the substrate, wherein

the second electrically conductive material is in electrical communication with the first electrically conductive material.

19. The method of claim 18, wherein:

the action of inserting the second electrically conductive material into the vais results in a hermetic barrier between a first side of the substrate and the second side of the substrate.

20. The method of claim 18, wherein:

the action of applying the first electrically conductive material includes hot-pressing a foil, corresponding to the electrically conductive material, onto the first face.

21. The method of claim 18, wherein:

the action of inserting the second electrically conductive material into the vias includes filling the vias with conductive material via electroplating.

22. The method of claim 18, wherein:

the action of inserting the second electrically conductive materials into the vias includes inserting an electrically conductive paste, thereby, along with the action of pressing the first electrically conductive material, establishing an embryonic feedthrough, the method further comprising;

firing the embryonic feedthrough.

23. The method of claim 18, wherein:

as a result of the application of the first electrically conductive material and the insertion of the second electrically conductive material, at least one via is in electrical communication with another via, the method further comprising;

removing one or more portions of the first electrically conductive material relative to the vias such that at least one via previously in electrical communication with another via is no longer in electrical communication with that via.

24. The method of claim 18, further comprising:

flip chip bonding a second substrate having an integrated circuit at least one of therein or thereon to the substrate having the vias such that the second conductive material is in electrical communication with the integrated circuit, via the bonding, and

establishing a hermetically enclosed volume in a space between the two substrates.

25. The method of claim 24, further comprising:

applying stud bumps to the second material in the vias so as to span a gap between components supported by the substrate having the vias and the integrated circuit.