DUPLICATE TAG STRUCTURE EMPLOYING SINGLE-PORT TAG RAM AND DUAL-PORT STATE RAM

• US 20150006803A1
• Filed: 06/27/2013
• Published: 01/01/2015
• Est. Priority Date: 06/27/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Kaushikkar, Harshavardhan, Kanchana, Muditha, Ewedemi, Odutola O.
• Granted Patent: US 9,454,482 B2
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a single-port memory, a dual-port memory, and a control circuit. The single-port memory may be store tag information associated with a cache memory, and the dual-port memory may be configured to store state information associated with the cache memory. The control circuit may be configured to receive a request which includes a tag address, access the tag and state information stored in the single-port memory and the dual-port memory, respectively, dependent upon the received tag address. A determination of if the data associated with the received tag address is contained in the cache memory may be made the control circuit, and the control circuit may update and store state information in the dual-port memory responsive to the determination.

Claims

1. An apparatus, comprising:

a single-port memory configured to store tag information associated with a cache memory;

a dual-port memory configured to store state information associated with the cache memory; and

a control circuit coupled to the single-port memory and the dual-port memory, wherein the control circuit is configured to;

receive a request, wherein the received request includes a tag address;

access the stored tag information in the single-port memory dependent upon the received tag address;

read the stored state information from the dual-port memory dependent upon the received tag address;

determine if data associated with the tag address is contained in the cache memory dependent upon the accessed stored tag information;

update the read state information dependent upon the determination that the data associated with the tag address is contained in the cache memory; and

store the updated state information in the dual-port memory.

2. The apparatus of claim 1, wherein to access the stored tag information in the single-port memory dependent upon the received tag address, the control circuit is further configured to store new tag information in the single-port memory dependent upon the received tag address.

3. The apparatus of claim 2, wherein the single-port memory is further configured to store one or more parity bits.

4. The apparatus of claim 1, wherein the single-port memory comprises a static random access memory (SRAM).

5. The apparatus of claim 1, wherein the dual-port memory comprises a static random access memory (SRAM).

6. The apparatus of claim 1, wherein to if data associated with the tag address is contained in the cache memory dependent upon the accessed stored tag information, the control circuit is further configured to send a response.

7. The apparatus of claim 1, wherein the single-port memory includes a parity bit associated with each entry in the single-port memory.

8. A method for operating a duplicate tag unit, comprising:

receiving a request, wherein the request includes a tag address;

accessing one or more tag memories dependent upon the received tag address, wherein each tag memory of the one or more tag memories contains tag information for a respective one of one or more cache memories;

reading state information from one or more state memories dependent upon the received tag address;

determining if data associated with the received tag address is contained in the one or more cache memories; and

updating the read state information dependent upon the determination that the data associated with the received tag address is included in the one or more cache memories.

9. The method of claim 8, wherein receiving the request comprises selecting an input source from a plurality of input sources.

10. The method of claim 9, wherein the plurality of inputs sources comprises a configuration interface, and a current transaction table (CTT).

11. The method of claim 8, wherein accessing the one or more tag memories comprises retrieving previously stored tag information from at least one of the one or more tag memories.

12. The method of claim 8, wherein accessing the one or more tag memories comprises storing tag information into at least one of the one or more tag memories.

13. The method of claim 8, wherein each of the one or more tag memories comprises a single-port memory.

14. The method of claim 8, wherein each of the one or more state memories comprises a dual-port memory.

15. A system, comprising:

a memory;

a coherency unit coupled to the memory; and

one or more processors coupled to the coherency unit, wherein each of the one or more processors includes a cache memory;

wherein the coherency unit includes;

one or more tag memories, wherein each one of the one or more tag memories is configured to store tag information for a respective cache memory of the one or more processors;

one or more state memories, wherein each one of the one or more state memories is configured to store state information for a respective cache memory of the one or more processors;

a control circuit configured to;

receive a request, wherein the received request includes a tag address;

access the tag information stored in the one or more tag memories dependent upon the received tag address;

read state information from the one or more state memories dependent upon the received tag address;

determine if the received tag address is contained in the one or more cache memories; and

updating the read state information dependent upon the determination that the received tag address is included in the one or more cache memories.

16. The system of claim 15, wherein each tag memory of the one or more tag memories comprises a single-port memory.

17. The system of claim 15, wherein each state memory of the one of more state memories comprises a dual-port memory.

18. The system of claim 15, wherein to determine if the received tag address is contained in the one or more cache memories, the control circuit is further configured to check the parity of the accessed tag information.

19. The system of claim 15, wherein to determine if the received tag address is contained in the one or more cache memories, the control circuit is further configured to send a response to the received request.

20. The system of claim 15, wherein the control circuit further includes a multiplex circuit, wherein the multiplex circuit is configured to select between one of a plurality of input sources.