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HYBRID MULTI-LEVEL MEMORY ARCHITECTURE

  • US 20150006805A1
  • Filed: 06/28/2013
  • Published: 01/01/2015
  • Est. Priority Date: 06/28/2013
  • Status: Active Grant
First Claim
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1. A system on chip (SoC) comprising:

  • a plurality of functional units; and

    a multi-level memory controller (MLMC) for a hybrid multi-level memory architecture comprising a first-level dynamic random access memory (DRAM) that is located on-package of the SOC and a second-level DRAM that is located off-package of the SOC,wherein the MLMC is coupled to the plurality of functional units,wherein the MLMC is to present the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and to provide the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM, andwherein the first-level DRAM does not store a copy of contents of the second-level DRAM.

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