HYBRID MULTI-LEVEL MEMORY ARCHITECTURE

• US 20150006805A1
• Filed: 06/28/2013
• Published: 01/01/2015
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Ariel Berkovits, Blaise fanning, Dannie G. Feekes, Eran Shifer, Evgeny Bolotin, Joydeep Ray, Julius Mandelblat, Shlomo Raikin
• Inventors: RAIKIN, SHLOMO, FANNING, BLAISE, RAY, JOYDEEP, GREENFIELD, ZVIKA, FEEKES, DANNIE G., MANDELBLAT, JULIUS, BERKOVITS, ARIEL, SHIFER, ERAN, BOLOTIN, EVGENY
• Granted Patent: US 9,734,079 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/063 for I/O modules, e.g. memory mapped I/O I/O protocol G06F13/42
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/206 Memory mapped I/O
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Claims

1. A system on chip (SoC) comprising:

a plurality of functional units; and

a multi-level memory controller (MLMC) for a hybrid multi-level memory architecture comprising a first-level dynamic random access memory (DRAM) that is located on-package of the SOC and a second-level DRAM that is located off-package of the SOC,

wherein the MLMC is coupled to the plurality of functional units,

wherein the MLMC is to present the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and to provide the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM, and

wherein the first-level DRAM does not store a copy of contents of the second-level DRAM.

2. The SOC of claim 1, wherein the first-level memory is a first memory type and the second-level memory is a second memory type.

3. The SOC of claim 2, wherein the first memory type is at least one of lower power per bandwidth than the second memory type, lower latency than the second memory type, or higher peak bandwidth than the second memory type.

4. The SOC of claim 1, wherein the MLMC is to:

receive memory requests from the plurality of functional units; and

map the memory requests to the first-level DRAM or the second-level DRAM according to a memory management scheme, wherein the memory management scheme is based on at least one of a bandwidth, a latency, a power requirement of a requesting one of the plurality of functional units.

5. The SOC of claim 1, wherein the MLMC is to operate as a cache controller that manages the first-level DRAM as a hardware-managed cache, and wherein the MLMC is to determine which of the first-level DRAM or the second-level DRAM the memory requests resides through a cache lookup, wherein the hardware-managed cache does not store a copy of contents of the second-level DRAM.

6. The SOC of claim 1, wherein the MLMC is to map a first set of memory pages accessed by one or more of the plurality of functional units in the first-level DRAM and a second set of memory pages accessed by one or more of the plurality of functional units in the second-level DRAM, wherein the first set of memory pages are accessed more frequently than the second set of memory pages.

7. The SOC of claim 1, wherein the MLMC is further to:

receive a memory request from one of the plurality of functional units;

identify a source identifier of the memory request; and

map the memory request to the first-level DRAM or the second-level DRAM according to a memory management scheme, wherein the memory management scheme is based at least in part on the source identifier.

8. The SOC of claim 1, wherein the MLMC is further to:

receive a memory request from one of the plurality of functional units, wherein the memory request corresponds to at least one of a dedicated load instruction or a dedicated store instruction that identifies one of the first-level DRAM or the second-level DRAM; and

map the memory request to the first-level DRAM or the second-level DRAM according to the one of the first-level DRAM or the second-level DRAM identified in the at least one of the dedicated load instruction or the dedicated store instruction.

9. The SOC of claim 1, wherein the MLMC is further to:

receive performance stall information of a previous memory request to a logical address that is mapped to a first physical address in the second-level DRAM; and

re-map the logical address to a second physical address in the first-level DRAM in response to the performance stall information.

10. The SOC of claim 1, wherein each system-addressable memory blocks of the contiguous addressable memory space resides in only one of the first-level DRAM or the second-level DRAM at any given time.

11. The SOC of claim 1, wherein the hybrid multi-level memory architecture is a pointer-based, non-inclusive memory architecture.

12. The SOC of claim 1, wherein the MLMC is further to:

identify a first memory page currently residing in the second-level DRAM to be relocated to the first-level DRAM;

identify a second memory page in the first-level DRAM to be swapped with the first memory page; and

swap the second memory page with the first memory page.

13. The SOC of claim 1, wherein the contiguous addressable memory space is divided into sets and ways, wherein for each set, a first portion of the ways reside in the first-level DRAM and a second portion of the ways reside in the second-level DRAM, wherein a first number of ways in the first portion over a second number of ways in the second portion is proportional to a ratio of the additional memory capacity of the first-level DRAM to the memory capacitive of the second-level DRAM.

14. The SOC of claim 1, wherein the first-level memory is embedded DRAM (eDRAM).

15. The SOC of claim 1, wherein the first-level memory is wide input-output (I/O) 2 (WIO2) DRAM.

16. The SOC of claim 1, wherein the second-level memory is at least one of low-power double data rate 3 (LPDDR3) DRAM, LPDDR4 DRAM, DDR3 DRAM, DDR3L DRAM, or DDR4 DRAM.

17. A processor comprising

a system interconnect for a multi-level memory (MLM) architecture comprising near memory that is located on-package of the processor and far memory that is located off-package of the processor, wherein the near memory is a first-level random access memory (RAM) and the far memory is a second-level RAM, wherein the system interconnect comprises:

a first near-memory controller to interface to a first near-memory device of the near memory;

a second near-memory controller to interface to a second near-memory device of the near memory;

a first far-memory controller to interface to a first far-memory device of the far memory;

a second far-memory controller to a second far-memory device of the far memory;

a far-memory arbitrator (FMARB) unit coupled to the first far-memory controller and the second far-memory controller;

a first MLM controller (MLMC) coupled to the first near memory controller and the FMARB unit; and

a second MLMC coupled to the second near memory controller and the FMARB unit.

18. The processor of claim 17, further comprising:

a plurality of functional hardware units coupled to the first MLMC and the second MLMC; and

a system agent coupled between the plurality of functional hardware units and the first MLMC and the second MLMC.

19. The processor of claim 17, wherein the first near-memory controller comprises two memory channels, wherein the second near-memory controller comprises two memory channels, wherein the first far-memory controller comprises a first memory channel and the second far-memory controller comprises a second memory channel.

20. The processor of claim 19, wherein the first memory channel comprises a first capacity that is different than a second capacity of the second memory channel.

21. The processor of claim 17, wherein a memory space of the multi-level memory (MLM) memory architecture is equally distributed between the first MLMC and the second MLMC, wherein the memory space is interleaved between the first MLMC and the second MLMC per a memory block size, and wherein a total far-memory capacity is equally divided to the first MLMC and the second MLMC.

22. A method comprising:

presenting to software, by a multi-level memory controller (MLMC), a contiguous addressable memory space of a hybrid multi-level memory architecture, wherein the hybrid multi-level memory architecture comprises a first-level dynamic random access memory (DRAM) that is located on-package and a second-level DRAM that is located off-package, wherein the first-level DRAM does not store a copy of contents of the second-level DRAM;

receiving a memory request at the MLMC from one of a plurality of functional units; and

mapping the memory request to the first-level DRAM or the second-level DRAM according to a memory management scheme.

23. The method of claim 22, wherein the memory management scheme is based on at least one of a bandwidth, a latency, a power requirement of a requesting one of the plurality of functional units.

24. The method of claim 22, wherein the mapping comprises:

mapping a first set of memory pages accessed by one or more of the plurality of functional units in the first-level DRAM; and

mapping a second set of memory pages accessed by one or more of the plurality of functional units in the second-level DRAM, wherein the first set of memory pages are accessed more frequently than the second set of memory pages.

25. The method of claim 22, further comprising:

identifying a first memory page currently residing in the second-level DRAM to be relocated to the first-level DRAM;

identifying a second memory page in the first-level DRAM to be swapped with the first memory page; and

swapping the second memory page with the first memory page.