GENERATION-BASED MEMORY SYNCHRONIZATION IN A MULTIPROCESSOR SYSTEM WITH WEAKLY CONSISTENT MEMORY ACCESSES

• US 20150006840A1
• Filed: 07/01/2014
• Published: 01/01/2015
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ohmacht, Martin
• Granted Patent: US 9,733,831 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/522 Barrier synchronisation
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Claims

1. A method for memory synchronization for use in a multiprocessor system, the method comprising carrying out operations in at least one data processing device, the operations comprising:

broadcasting a central generation indication from a memory synchronization unit; and

delaying memory access requests responsive to values of the central generation indication.

2. The method of claim 1, wherein the operations comprise

tagging memory access requests responsive to the central access indication;

OR-ing bits from results of tagging to determine what generations are in flight; and

supplying a value responsive to a result of the OR-ing to a unit requesting memory synchronization.

3. The method of claim 1, wherein

the central generation indication comprises a pointer value and

the operations comprise,

holding incrementation of the pointer value so long as a given generation is in flight;

and

when given generations in flight are completed, incrementing the pointer value.

4. The method of claim 1, wherein the central indication comprises a first count indicating a generation and a second count indicating a reclaim pointer.

5. The method of claim 4, comprising preventing the first and second count from passing each other.

6. A central memory synchronization module for use in a multiprocessor system, the system comprising a plurality of processors, the module comprising

at least one global generation unit for storing a global numeric generation indication;

at least one global or-reduce tree, for aggregating information about current generations of memory requests in flight; and

at least one broadcast facility for broadcasting the generation indication and a result derived from the tree.

7. The module of claim 6,

wherein the global generation unit comprises:

a counter for defining a current generation of memory access; and

a reclaim pointer for pointing to an oldest generation in flight; and

further comprising;

at least one interface unit for coupling with at least one device control register bus;

at least one broadcast interface for providing a value of the counter and the reclaim pointer to the system; and

a request interface for coupling within the system and receiving synchronization requests.

8. The module of claim 6, wherein the global OR reduce tree comprises:

means for receiving a plurality of respective vectors—

each respective vector having a respective bit for each possible generation, indicating whether there are memory accesses in flight for that generation—

from each unit capable of requesting memory access; and

at least one means for OR-ing the respective vectors to determine whether there are memory access requests in flight for any generation.

9. A system comprising

the module of claim 6 and

at least one interface unit for coupling with a synchronization requesting processor and an OR reduce end-point of the global generation unit, the interface unit including a plurality of respective generation detectors.