KEYBOARD CIRCUIT

• US 20150006920A1
• Filed: 08/27/2013
• Published: 01/01/2015
• Est. Priority Date: 06/28/2013
• Status: Abandoned Application

• Current Assignee: FIH (Hong Kong) Limited (Hon Hai Precision Industry Co., Ltd.), Shenzhen Futaihong Precision Industrial Company Limited (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: FIH (Hong Kong) Limited (Hon Hai Precision Industry Co., Ltd.), Shenzhen Futaihong Precision Industrial Company Limited (Hon Hai Precision Industry Co., Ltd.)
• Inventors: LI, JIAN-HUI
• Application Number:
  US14/010,553
• Publication Number:
  US 20150006920A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 3/023 Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry

Abstract

A keyboard circuit includes a CPU, a plurality of keys aligned in n rows and m columns, n first resistors, m second resistors, a first voltage output terminal, a second voltage output terminal, and a detection resistor. A first contact of each of the plurality of keys in a column is electronically connected to the first voltage output terminal by a second resistor, and a second contact of each of the plurality of keys in the column is grounded by the detection resistor. The first contact of each of the plurality of keys in a row is electronically connected to the second voltage output terminal by a first resistor. The CPU is grounded by the detection resistor and the first voltage output terminal alternates with the second voltage output terminal to output a voltage under control of the CPU.

Claims

1. A keyboard circuit, comprising:

a central processing unit (CPU);

a plurality of keys aligned in a matrix fashion of n rows and m columns, where n and m are natural numbers;

n first resistors corresponding to the n rows keys;

m second resistors corresponding to the m columns keys;

a first voltage output terminal;

a second voltage output terminal; and

a detection resistor;

wherein a first contact of each of the plurality of keys aligned in a same column is electronically connected to the first voltage output terminal by a corresponding second resistor, a second contact of each of the plurality of keys aligned in the same column is grounded by the detection resistor;

the first contact of each of the plurality of keys aligned in a same row is electronically connected to the second voltage output terminal by a corresponding first resistor;

the CPU is grounded by the detection resistor and the first voltage output terminal alternates with the second voltage output terminal to output a voltage under control of the CPU.

2. The keyboard circuit as claimed in claim 1, wherein the CPU stores first reference voltages corresponding to the n rows and second reference voltages corresponding to the m columns;

a voltage variation of the detection resistor raises an interrupt in the CPU and the CPU measures the voltage of the detection resistor and compares the voltage of the detection resistor with the first reference voltages and the second reference voltages to determine a location of a pressed key.

3. The keyboard circuit as claimed in claim 1, wherein resistances of the first resistors and resistances of the second resistors are not equal.

4. The keyboard circuit as claimed in claim 1, wherein the CPU comprises an analog to digital terminal which is grounded by the detection resistor.

5. The keyboard circuit as claimed in claim 1, wherein the first voltage output terminal and the second voltage output terminal are two terminals of a power supply chip, and the power supply chip is electronically connected to the CPU.

6. The keyboard circuit as claimed in claim 1, wherein the first voltage output terminal is an output terminal of a first power source, and the second voltage output terminal is an output terminal of a second power source;

the first power source and the second power source are electronically connected to the CPU.

7. A keyboard circuit, comprising:

a central processing unit (CPU);

a plurality of keys aligned in a matrix fashion of n rows and m columns, n and m are natural numbers;

n first resistors corresponding to the n rows;

m second resistors corresponding to the m columns;

a first voltage output terminal electronically connected the m second resistors;

a second voltage output terminal electronically connected the n first resistors; and

a detection resistor;

wherein each first resistor is connected to the detection resistor by any one of the keys located in a same row with the first resistor;

each second resistor is connected to the detection resistor by any one of the keys located in a same column with the second resistor;

the CPU is grounded by the detection resistor and the first voltage output terminal alternates with the second voltage output terminal to output a voltage under control of the CPU.

8. The keyboard circuit as claimed in claim 7, wherein the CPU stores first reference voltages corresponding to the n rows and second reference voltages corresponding to the m columns;

a voltage variation of the detection resistor raises an interrupt in the CPU and the CPU measures the voltage of the detection resistor and compares the voltage of the detection resistor with the first reference voltages and the second reference voltages to determine a location of a pressed key.

9. The keyboard circuit as claimed in claim 7, wherein resistances of the first resistors and resistances of the second resistors are not equal.

10. The keyboard circuit as claimed in claim 7, wherein the CPU comprises an analog to digital terminal which is grounded by the detection resistor.

11. The keyboard circuit as claimed in claim 7, wherein the first voltage output terminal and the second voltage output terminal are two terminals of a power supply chip, and the power supply chip is electronically connected to the CPU.

12. The keyboard circuit as claimed in claim 7, wherein the first voltage output terminal is an output terminal of a first power source, and the second voltage output terminal is an output terminal of a second power source;

the first power source and the second power source are electronically connected to the CPU.

13. A keyboard circuit, comprising:

a central processing unit (CPU) comprising a first voltage output terminal and a second voltage output terminal;

a plurality of keys aligned in a matrix fashion of n rows and m columns, n and m are natural numbers;

n first resistors corresponding to the n rows;

m second resistors corresponding to the m columns; and

a detection resistor;

wherein a first contact of each of the plurality of keys aligned in a same column is electronically connected to the first voltage output terminal by a corresponding second resistor, a second contact of each of the plurality of keys aligned in the same column is grounded by the detection resistor;

the first contact of each of the plurality of keys aligned in a same row is electronically connected to the second voltage output terminal by a corresponding first resistor;

the CPU is grounded by the detection resistor and the first voltage output terminal alternates with the second voltage output terminal to output a voltage under control of the CPU.

14. The keyboard circuit as claimed in claim 13, wherein the CPU stores first reference voltages corresponding to the n rows and second reference voltages corresponding to the m columns;

a voltage variation of the detection resistor raises an interrupt in the CPU and the CPU measures the voltage of the detection resistor and compares the voltage of the detection resistor with the first reference voltages and the second reference voltages to determine a location of a pressed key.

15. The keyboard circuit as claimed in claim 13, wherein resistances of the first resistors and resistances of the second resistors are not equal.

16. The keyboard circuit as claimed in claim 13, wherein the CPU comprises an analog to digital terminal which is grounded by the detection resistor.