COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS

• US 20150006987A1
• Filed: 09/16/2014
• Published: 01/01/2015
• Est. Priority Date: 06/11/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Narayanan, Prakash, Subramanian, Sundarrajan, Parekhji, Rubin A., Jain, Arvind
• Granted Patent: US 9,091,729 B2
• Time in Patent Office: Days
• US Class Current: 714/729
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Claims

1. Electronic scan circuitry comprising:

a decompressor;

a plurality of scan chains fed by the decompressor;

a scan circuit coupled to the plurality of scan chains to scan them in and out;

a masking circuit fed by the scan chains;

a scannable masking qualification circuit coupled to the masking circuit, the masking qualification circuit scannable by scan-in of bits by the decompressor along with scan-in of the scan chains, and the scannable masking qualification circuit operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit; and

bit-field decoders wherein the scannable masking qualification circuit has a shift register fed by the decompressor and including sets of shift register cells, each set operable to couple a bit-field to a corresponding one of the bit-field decoders, each one such decoder having a decode output coupled to the masking circuit to independently select at least one scan chain for qualification in a distinct respective group among the scan chains for each one such decoder corresponding to each such set of shift register cells in the shift register.

2. The electronic scan circuitry of claim 1 in which each set of shift register cells is operable to couple a bit-field to a corresponding one of the bit-field decoders equal to a binary difference of each chain number i of the scan chain to be observed less a base value for a group of the scan chains in which that scan chain lies.