METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE AND THIN FILM TRANSISTOR SUBSTRATE MANUFACTURED BY THE METHOD

• US 20150008429A1
• Filed: 01/16/2013
• Published: 01/08/2015
• Est. Priority Date: 01/23/2012
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ito, Kazuatsu, Kitakado, Hidehito
• Granted Patent: US 9,209,282 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention includes at least a step forming a source electrode (32) and a drain electrode (33), each of which is a multilayer film of a first conductive film (32a), (33a) made of titanium or molybdenum, a second conductive film (32b), (33b) made of copper, and a third conductive film (32c), (33c) made of titanium oxide, a step of forming passivation film (18), which is an inorganic insulating film, on an oxide semiconductor layer (13), the source electrode (32) and drain electrode (33), and an annealing step of annealing the oxide semiconductor layer (13).

Claims

1. A method of manufacturing a thin film transistor substrate including

an insulating substrate,

an oxide semiconductor layer provided on the insulating substrate and having a channel region,

a source electrode and a drain electrode provided on the oxide semiconductor layer to face one another with the channel region interposed therebetween, and

a passivation film covering the oxide semiconductor layer, the source electrode, and the drain electrode,

the method comprising at least:

a semiconductor layer forming step of forming the oxide semiconductor layer on the insulating substrate;

a source/drain forming step of forming the source electrode and the drain electrode, each of which is a multilayer film of a first conductive film provided on the oxide semiconductor layer and made of titanium or molybdenum, a second conductive film provided on the first conductive film and made of copper, and a third conductive film provided on the second conductive film and made of titanium oxide;

a passivation film forming step of forming the passivation film which is an inorganic insulating film on the oxide semiconductor layer, the source electrode, and the drain electrode; and

an annealing step of annealing the oxide semiconductor layer.

2. The method of claim 1, wherein

in the source/drain forming step, the titanium oxide forming the third conductive film is formed by thermal treatment or plasma treatment of a titanium film formed on the second conductive film.

3. The method of claim 1, wherein

the third conductive film has a thickness ranging from 5 nm to 10 nm.

5. The method of claim 1, wherein

the oxide semiconductor layer is made of metal oxide containing at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn).

6. The method of claim 5, wherein

the oxide semiconductor layer is made of indium gallium zinc oxide.

7. A thin film transistor substrate manufactured by the method of claim 1.

4. A method of manufacturing a thin film transistor substrate including

an insulating substrate,

an oxide semiconductor layer provided on the insulating substrate and having a channel region,

a source electrode and a drain electrode provided on the oxide semiconductor layer to face one another with the channel region interposed therebetween, and

a passivation film covering the oxide semiconductor layer, the source electrode, and the drain electrode,

the method comprising at least:

a semiconductor layer forming step of forming the oxide semiconductor layer on the insulating substrate;

a metal film forming step of forming a first conductive film provided on the oxide semiconductor layer and made of titanium or molybdenum, a second conductive film provided on the first conductive film and made of copper, and a copper-titanium alloy film provided on the second conductive film and containing titanium within a range from 20 at % to 50 at %, both inclusive;

a passivation film forming step of forming a passivation film which is an inorganic insulating film on the oxide semiconductor layer, the first conductive film, the second conductive film, and the copper-titanium alloy film; and

a source/drain forming step of forming the source electrode and the drain electrode, each of which is a multilayer film of the first conductive film, the second conductive film, and a third conductive film including the copper-titanium alloy film and a titanium oxide film, by annealing the oxide semiconductor layer, and forming the titanium oxide film on the surface of the copper-titanium alloy film by the annealing.